SI3232-G-GQ Silicon Laboratories Inc, SI3232-G-GQ Datasheet - Page 49

• Manufacturer Part Number: SI3232-G-GQ
• Description: IC SLIC PROG DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3232-G-GQ

• Function: Subscriber Line Interface Concept (SLIC)
• Interface: ISDN
• Number Of Circuits: 2
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 28mA
• Power (watts): 280mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Product: Telecom
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The resulting gain levels using the ARX stage are
summarized in Table 30. All settings assume an
external codec with 475 Ω per leg of source impedance
driving the RX inputs differentially at VRXPa-VRXNa
(for channel a) or VRXPb-VRXNb (for channel b) to
achieve a 0 dBm0 TIP-RING audio output signal.
4.15. System Clock Generation
The Si3232 generates the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 786 kHz,
1.024 MHz,
4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to
the FSYNC rate is determined by a counter clocked by
PCLK. The 3-bit ratio information is automatically
transferred into an internal register, PLL_MULT,
following a device reset. PLL_MULT is used to control
the internal PLL, which multiplies PCLK as needed to
generate the rate required to run the internal filters and
other circuitry.
The PLL clock synthesizer settles quickly after powerup
ARXMUTE
PCLK
Setting
Table 30. ARX Attenuation Stage Settings
1
0
0
0
0
ARX[1:0]
1.536 MHz,
Setting
00
01
10
xx
11
PFD
RESET
Reserved. Do not use.
Typical TX Path Gain
1.544 MHz,
Mute (no T-R output)
–3.52 dB (G = 2/3)
–6.02 dB (G = 1/2)
0 dB (G = 1)
Figure 26. PLL Frequency Synthesizer
PLL_MULT
DIV M
2.048 MHz,
Preliminary Rev. 0.96
or update of the PLL-MULT register. The PLL lock
process begins immediately after the RESET pin is
pulled high and will take approximately 5 ms to achieve
lock after RESET is released with stable PCLK and
FSYNC. However, the settling time depends on the
PCLK frequency and can be predicted based on the
following equation:
t
Note: Therefore, the RESET pin must be held low during
4.15.1. Interrupt Logic
The Si3232 is capable of generating interrupts for the
following events:
The interface to the interrupt logic consists of six
registers. Three interrupt status registers (IRQ0–IRQ3)
contain one bit for each of the above interrupt functions.
These bits are set when an interrupt is pending for the
associated resource. Three interrupt mask registers
(IRQEN1–IRQEN3) also contain one bit for each
interrupt function. In the case of the interrupt mask
registers, the bits are active high. Refer to the
appropriate functional description text for operational
details of the interrupt functions.
SETTLE
Loop current/ring ground detected.
Ground key detected.
Ring trip detected.
Power alarm.
Ringing active timer expired.
Ringing inactive timer expired.
Pulse metering active timer expired.
Pulse metering inactive timer expired.
RAM address access complete.
VCO
powerup and should only be released when both PCLK
and FSYNC signals are known to be stable.
= 64 / f
PCLK
÷2
÷2
28.672 MHz
Si3232
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