SI3200-GS Silicon Laboratories Inc, SI3200-GS Datasheet - Page 59

• Manufacturer Part Number: SI3200-GS
• Description: IC LINEFEED INTRFC 100V 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3200-GS

• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 110µA
• Power (watts): 941mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

the appropriate coefficients for the FIR and IIR filter
blocks.
The transhybrid balance filters can be disabled to
implement loopback diagnostic modes. To disable the
transhybrid balance filter (zero cancellation), set the
HYBDIS bit in the DIGCON register to 1.
Note: The user must enter values into each register location
Tone Generators
Dual ProSLIC devices have two digital tone generators
that allow a wide variety of single or dual tone frequency
and amplitude combinations that spare the user the
effort of generating the required POTS signaling tones
on the PCM highway. DTMF, FSK (caller ID), call
progress, and other tones can all be generated on-chip.
The tones are sent to the receive or transmit paths.
(See Figure 11 on page 24.)
Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 35. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected for flexibility in creating audio signals.
Control and status register bits are placed in the figure
to indicate their association with the tone generator
to ensure correct operation when the hybrid balance
block is enabled.
Counter
OSCnTA
Modulo
OSCnTI
16-Bit
8 kHz
Clock
n = "1" or "2" for Tone Generator 1 and 2, respectively
OSCnTIEN
OSCnTAEN
OSCnTA
OSCnTI
OSCnEN
Expire
Expire
*Tone Generator 1 Only
Cross
Logic
Zero
Logic
Logic
INT
INT
Figure 35. Tone Generator Diagram
ZEROENn
ENSYNCn
Zero Cross
OSnTIS
Logic
Load
OSnTAS
OSnTIE
OSnTAE
REL*
Register
Enable
Load
Rev. 1.0
Two-Pole
Resonant
Oscillator
architecture. The register set for tone generation is
summarized in Table 34.
Oscillator Frequency and Amplitude
Each of the two tone generators contains a two-pole
resonant
frequency and amplitude, which are programmed via
RAM addresses OSC1FREQ, OSC1AMP, OSC1PHAS,
OSC2FREQ, OSC2AMP, and OSC2PHAS. The sample
rate for the two oscillators is 8000 Hz. The equations
are as follows:
where f
where Desired Vrms is the amplitude to be generated;
n = 1 or 2 for oscillator 1 or oscillator 2, respectively.
For example, to generate a DTMF digit of 8, the two
required tones are 852 Hz and 1336 Hz. Assuming we
want to generate half-scale values (ignoring twist), the
following values are calculated:
8 kHz
Clock
OSCnAMP
OSCnFREQ
OSCnPHAS
OSCnAMP
n
is the frequency to be generated;
oscillator
OSCnFREQ = coeff
coeff
=
1
-- - 1 coeff
4
n
----------------------- -
1
OSCnPHAS = 0,
= cos(2 π f
–
+
coeff
circuit
Si3220/Si3225
Routing
Signal
×
(
n
2
with
/8000 Hz),
15
n
–
ROUTn
x (2
1
)
a
×
14
Desired Vrms
--------------------------------------- -
);
programmable
1.11 Vrms
to RX Path
to TX Path
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