RC28F128P33BF60A Micron Technology Inc, RC28F128P33BF60A Datasheet - Page 53

• Manufacturer Part Number: RC28F128P33BF60A
• Manufacturer: Micron Technology Inc

Specifications of RC28F128P33BF60A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

P33-65nm SBC
Figure 21: Continuous Burst Read, showing an Output Delay Timing
Notes:
1.
2.
Figure 22: Synchronous Burst-Mode Four-Word Read Timing
Note:
Datasheet
53
Address [A]
Data [D/Q]
Address [A]
Data [D/Q]
ADV# [V]
WAIT [T]
ADV# [V]
OE# [G]
WAIT [T]
CLK [C]
CE# [E]
OE# [G]
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned. See
page 36
WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR.10=0, WAIT asserted low).
CLK [C]
CE# [E]
for more information.
R105
R105
R105
R105
R301
R301
R302
R303
R302
R303
R101
R101
R102
R102
A
R306
R306
R15
R106
R106
R15
R2
R3
R7
R2
R7
R3
Section 11.1.3, “End of Word Line (EOWL) Considerations” on
R4
R4
y
R307
R304
R307
R304
Q0
R312
R305
R305
R304
Q1
R305
R304
Q2
R305
R304
Order Number:208034-04
Q3
R17
R9
R10
R8
R304
R305
Jul 2011