ADV3000ASTZ-RL Analog Devices Inc, ADV3000ASTZ-RL Datasheet - Page 14

• Manufacturer Part Number: ADV3000ASTZ-RL
• Description: IC HDMI/DVI SWITCH 3.1 80LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADV3000ASTZ-RL

• Function: Switch
• Circuit: 1 x 3:1
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 3 V ~ 3.6 V
• Current - Supply: 110mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV3000
SERIAL CONTROL INTERFACE
RESET
On initial power-up, or at any point in operation, the ADV3000
register set can be restored to preprogrammed default values by
pulling the RESET pin to low in accordance with the specifica-
tions in Table 1. During normal operation, however, the RESET
pin must be pulled up to 3.3 V. Following a reset, the prepro-
grammed default values of the ADV3000 register set correspond
to the state of the parallel interface configuration registers, as
listed in Table 18. The ADV3000 can be controlled through the
parallel control interface until the first serial control event
occurs. As soon as any serial control event occurs, the serial
programming values, corresponding to the state of the serial
interface configuration registers (Table 5), override any prior
parallel programming values, and the parallel control interface
is disabled until the part is subsequently reset.
WRITE PROCEDURE
To write data to the ADV3000 register set, an I
as a microcontroller) needs to send the appropriate control
signals to the ADV3000 slave device. The signals are controlled
by the I
the procedure, see Figure 29. The steps for a write procedure are
as follows:
1.
2.
3.
Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
Send the ADV3000 part address (seven bits). The upper six
bits of the ADV3000 part address are the static value
[100100] and the LSB is set by Input Pin I2C_ADDR0. This
transfer should be MSB first.
Send the write indicator bit (0).
GENERAL CASE
2
C master, unless otherwise specified. For a diagram of
EXAMPLE
I2C_SDA
I2C_SDA
I2C_SCL
*THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE LAST
DATA BIT; FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP 8.
START
1
2
FIXED PART
ADDR
I2C_ADDR0
2
C master (such
R/W
3
Figure 29. I
ACK
4
Rev. 0 | Page 14 of 28
5
2
C Write Diagram
REGISTER ADDR
4.
5.
6.
7.
8.
9.
Wait for the ADV3000 to acknowledge the request.
Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
Wait for the ADV3000 to acknowledge the request.
Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.
Wait for the ADV3000 to acknowledge the request.
Perform one of the following:
9a. Send a stop condition (while holding the I2C_SCL
9b. Send a repeated start condition (while holding the
9c. Send a repeated start condition (while holding the
9d. Send a repeated start condition (while holding the
line high, pull the I2C_SDA line high) and release
control of the bus to end the transaction (shown in
Figure 29).
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 in this procedure to perform
another write.
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the read procedure (in the
Read Procedure section) to perform a read from
another address.
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of the read procedure (in the
Read Procedure section) to perform a read from the
same address set in Step 5.
ACK
6
7
DATA
*
ACK
8
STOP
9