S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 233

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

5: INTERFACING TO THE TOSHIBA MIPS TMPR3912 MICROPROCESSOR
Memory Mapping and Aliasing
5-32
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Note: See Section , “Host Bus Pin Connection” on page 5-29 and Section , “Generic #2 Interface
The “Generic #2” host interface control signals of the S1D13705 are asynchronous with respect to
the S1D13705 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13705 clock frequencies.
The S1D13705 also has internal clock dividers providing additional flexibility.
In this example implementation the TMPR3912 control signal CARDREG* is ignored; therefore the
S1D13705 takes up the entire PC Card slot 1.
The S1D13705 requires an addressing space of 128K bytes. The on-chip display memory occupies
the range 0 through 13FFFh. The registers occupy the range 1FFE0h through 1FFFFh. The
TMPR3912 demultiplexed address lines A17 and above are ignored, thus the S1D13705 is aliased
512 times at 128K byte intervals over the 64M byte PC Card slot #1 memory space.
Note: If aliasing is undesirable, additional decoding circuitry must be added.
ENDIAN
CARD1WAIT*
CARD1CSH*
CARDIORD*
CARDIOWR*
CARD1CSL*
TMPR3912
DCLKOUT
Mode” on page 5-26 for Generic #2 pin descriptions.
D[31:24]
D[23:16]
A[12:0]
ALE
Figure 5-1 S1D13705 to TMPR3912 Direct Connection
Latch
V
Clock divider
DD
pull-up
EPSON
...or...
Oscillator
System RESET
+3.3V
+3.3V
S1D13705F00A APPLICATION NOTES
+3.3V
See text
BS#
RD/WR#
IO V
RD#
WE0#
WE1#
CLKI
BCLK
AB[16:13]
AB[12:0]
DB[7:0]
DB[15:8]
WAIT#
RESET#
CS#
S1D13705
DD
, CORE V
(X27A-G-004-01)
DD