S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 213

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
Host Bus Interface Modes
Generic #1 Host Bus Interface Mode
5-12
For details on configuration, refer to the “S1D13705 Hardware Functional Specification”,
document number X27A-A-001-01.
Generic #1 host bus interface mode is the most general and least processor-specific host bus
interface mode on the S1D13705. The Generic # 1 host bus interface mode was chosen for this
interface due to the simplicity of its timing.
The host bus interface requires the following signals:
• BUSCLK is a clock input which is required by the S1D13705 host interface. It is separate from
• The address inputs AB0 through AB16, and the data bus DB0 through DB15, connect directly to
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper IO or
• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively, to be
• WAIT# is a signal output from the S1D13705 that indicates the host CPU must wait until data is
• The Bus Status (BS#) signal is not used in the bus interface for Generic #1 mode. However, BS# is
the input clock (CLKI) and is typically driven by the host CPU system clock.
the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power
PC, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big
endian hosts, they would connect to the low-order data lines. The hardware engineer must ensure
that CNF3 selects the proper endian mode upon reset.
memory address space.
driven low when the host CPU is writing data to the S1D13705.
driven low when the host CPU is reading data from the S1D13705.
ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the
S1D13705 may occur asynchronously to the display update, it is possible that contention may
occur in accessing the S1D13705 internal registers and/or refresh memory. The WAIT# line
resolves these contentions by forcing the host to wait until the resource arbitration is complete.
This signal is active low and may need to be inverted if the host CPU wait state signal is active
high.
used to configure the S1D13705 for Generic #1 mode and should be tied low (connected to GND).
Table 2-1 Host Bus Interface Pin Mapping
Pin Names
S1D13705
AB[15:1]
DB[15:0]
RD/WR#
RESET#
WAIT#
BCLK
WE1#
WE0#
AB0
RD#
CS#
BS#
EPSON
External Decode
connect to V
Generic #1
RESET#
A[15:1]
D[15:0]
WAIT#
BCLK
WE1#
WE0#
RD1#
RD0#
A0
SS
S1D13705F00A APPLICATION NOTES
(X27A-G-010-01)