LSM303DLHC STMicroelectronics, LSM303DLHC Datasheet - Page 33

• Manufacturer Part Number: LSM303DLHC
• Manufacturer: STMicroelectronics

Specifications of LSM303DLHC

• Lead Free Status / Rohs Status: Compliant

LSM303DLHC
7.1.20
7.1.21
Table 53.
Interrupt 2 source register. Read only register.
Reading at this address clears INT2_SRC IA bit (and the interrupt signal on the INT 2 pin)
and allows the refreshing of data in the INT2_SRC register if the latched option was chosen.
INT2_THS_A (36h)
Table 54.
1. This bit must be set to ‘0’ for correct working of the device
Table 55.
INT2_DURATION_A (37h)
Table 56.
1. This bit must be set to ‘0’ for correct working of the device
Table 57.
IA
ZH
ZL
YH
YL
XH
XL
THS6 - THS0
D6-D0
0
0
(1)
(1)
Interrupt active. Default value: 0
(0: no interrupt has been generated, 1: one or more interrupts have been generated)
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
Z low. Default value: 0
(0: no interrupt, 1: Z low event has occurred)
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
X Low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
INT2_SRC_A description
INT2_THS_A register
INT2_THS_A description
INT2_DURATION_A register
INT2_DURATION_A description
THS6
D6
Interrupt 1 threshold. Default value: 000 0000
Duration value. Default value: 000 0000
THS5
D5
Doc ID 018771 Rev 1
THS4
D4
THS3
D3
THS2
D2
Register description
THS1
D1
THS0
D0
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