LSM303DLHC STMicroelectronics, LSM303DLHC Datasheet - Page 31

• Manufacturer Part Number: LSM303DLHC
• Manufacturer: STMicroelectronics

Specifications of LSM303DLHC

• Lead Free Status / Rohs Status: Compliant

LSM303DLHC
7.1.16
7.1.17
7.1.18
Table 44.
Interrupt 1 source register. Read only register.
Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1
pin) and allows the refreshing of data in the INT1_SRC register if the latched option was
chosen.
INT1_THS_A (32h)
Table 45.
1. This bit must be set to ‘0’ for correct working of the device.
Table 46.
INT1_DURATION_A (33h)
Table 47.
1. This bit must be set to ‘0’ for correct working of the device.
Table 48.
D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. Duration
steps and maximum values depend on the ODR chosen.
INT2_CFG_A (34h)
Table 49.
D6 - D0
THS6 - THS0
XH
YL
XL
AOI
0
0
(1)
(1)
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
INT1_SRC_A description (continued)
INT1_THS_A register
INT1_THS_A description
INT1_DURATION_A register
INT1_DURATION_A description
INT2_CFG_A register
THS6
D6
6D
Interrupt 1 threshold. Default value: 000 0000
Duration value. Default value: 000 0000
THS5
ZHIE
D5
Doc ID 018771 Rev 1
THS4
ZLIE
D4
THS3
YHIE
D3
THS2
YLIE
D2
Register description
THS1
XHIE
D1
THS0
XLIE
D0
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