AD7609BSTZ Analog Devices Inc, AD7609BSTZ Datasheet - Page 27

• Manufacturer Part Number: AD7609BSTZ
• Description: 58T8900
• Manufacturer: Analog Devices Inc

Specifications of AD7609BSTZ

• Resolution (bits): 18bit
• Sampling Rate: 250kSPS
• Input Channel Type: Differential
• Data Interface: Serial, SPI
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Rohs Compliant: Yes

Figure 6 shows the timing diagram for reading one channel of
data, framed by the CS signal, from the
The SCLK input signal provides the clock source for the serial
read operation.
The falling edge of CS takes the bus out of three-state and
clocks out the MSB of the 18-bit conversion result. This MSB
is valid on the first falling edge of the SCLK after the CS falling
edge. The subsequent 17 data bits are clocked out of the
AD7609
falling edge. Eighteen clock cycles must be provided to the
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The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the CS input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of
CS takes FRSTDATA out of three-state and sets the FRSTDATA
pin high indicating that the result from V1 is available on the
D
logic low following the 18
OUT
A output data line. The FRSTDATA output returns to a
on the SCLK rising edge. Data is valid on the SCLK
to access each conversion result.
CS goes low to access the data from the AD7609.
th
SCLK falling edge. If all channels
D
D
SCLK
OUT
OUT
CS
A
B
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Figure 44.
in serial mode.
V1
V5
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Serial Interface with Two D
V2
V6
are read on D
when V1 is being output on this serial data output pin. It only
goes high when V1 is available on D
is available on D
READING DURING CONVERSION
Data can be read from the
and conversions are in progress. This has little effect on the
performance of the converter and allows a faster throughput
rate to be achieved. A parallel or serial read can be performed
during conversions and when oversampling may or may not
be in use. Figure 3 shows the timing diagram for reading while
BUSY is high in parallel or serial mode. Reading during conver-
sions allows the full throughput rate to be achieved when using
the serial interface with a V
Data can be read from the
the falling edge of BUSY because this is when the output data
registers are updated with the new conversion data. t
in Table 3, should be observed in this condition.
V3
V7
OUT
OUT
Lines
V4
V8
OUT
B, the FRSTDATA output does not go high
B).
72
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DRIVE
of 3.3 V to 5.25 V.
while BUSY is high
at any time other than on
OUT
A (and this is when V5
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6
, outlined