NUC130RE3CN Nuvoton Technology Corporation of America, NUC130RE3CN Datasheet - Page 479

• Manufacturer Part Number: NUC130RE3CN
• Description: IC MCU 32BIT 128KB FLASH 64LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130RE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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NuMicro™ NUC130/NUC140 Technical Reference Manual
DIFFEN
PTEN
TRGEN
TRGCOND
TRGS
Differential Input Mode Enable
1 = Differential analog input mode
0 = Single-end analog input mode
Differential input voltage (V
inverted analog input.
In differential input mode, only the even number of the two corresponding channels
needs to be enabled in ADCHER. The conversion result will be placed to the
corresponding data register of the enabled channel.
PDMA Transfer Enable
1 = Enable PDMA data transfer in ADDR 0~7
0 = Disable PDMA data transfer
When A/D conversion is completed, the converted data is loaded into ADDR 0~7,
software can enable this bit to generate a PDMA data transfer request.
When PTEN=1, software must set ADIE=0 to disable interrupt.
External Trigger Enable
Enable or disable triggering of A/D conversion by external STADC pin.
1= Enable
0= Disable
ADC external trigger function is only supported in single-cycle scan mode.
External Trigger Condition
These two bits decide external pin STADC trigger event is level or edge. The signal
must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and
low state for edge trigger.
00 = Low level
01 = High level
10 = Falling edge
11 = Rising edge
Hardware Trigger Source
00 = A/D conversion is started by external STADC pin.
Others = Reserved
Software should disable TRGEN and ADST before change TRGS.
In hardware trigger mode, the ADST bit is set by the external trigger from STADC.
Differential input paired channel
- 479 -
0
1
2
3
diff
) = V
plus
Publication Release Date: June 14, 2011
- V
minus
, where V
ADC0
ADC2
ADC4
ADC6
V
plus
ADC analog input
plus
is the analog input; V
ADC1
ADC3
ADC5
ADC7
V
Revision V2.01
minus
minus
is the