NUC130RE3CN Nuvoton Technology Corporation of America, NUC130RE3CN Datasheet - Page 315

• Manufacturer Part Number: NUC130RE3CN
• Description: IC MCU 32BIT 128KB FLASH 64LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130RE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

[28:27]
[26]
[25]
[24]
[23:17]
[16]
[15:8]
[7:0]
NuMicro™ NUC130/NUC140 Technical Reference Manual
MODE
CRST
CACT
CTB
Reserved
TDR_EN
Reserved
PRESCALE
up-timer value is equal to TCMPR.
Timer Operating Mode
Timer Reset Bit
Set this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to
0.
0 = No effect
1 = Reset Timer’s 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit
Timer Active Status Bit (Read only)
This bit indicates the up-timer status.
0 = Timer is not active
1 = Timer is active
Counter Mode Enable Bit
This bit is the counter mode enable bit. When Timer is used as an event counter, this
bit should be set to 1 and Timer will work as an event counter. The counter detect
phase can be selected as rising/falling edge of external pin by TX_PHASE field.
1 = Enable counter mode
0 = Disable counter mode
Reserved
Data Load Enable
When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the
24-bit up-timer value as the timer is counting.
1 = Timer Data Register update enable
0 = Timer Data Register update disable
Reserved
Pre-scale Counter
Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE =
0, then there is no scaling.
MODE
00
01
10
11
- 315 -
Timer Operating Mode
The timer is operating at the one-shot mode. The associated
interrupt signal is generated once (if IE is enabled) and CEN is
automatically cleared by hardware.
The timer is operating at the periodic mode. The associated
interrupt signal is generated periodically (if IE is enabled).
The timer is operating at the toggle mode. The interrupt signal is
generated periodically (if IE is enabled). And the associated
signal (tout) is changing back and forth with 50% duty cycle.
The timer is operating at continuous counting mode. The
associated interrupt signal is generated when TDR = TCMPR (if
IE is enabled). However, the 24-bit up-timer counts continuously.
Please refer 5.10.4.4 for detail description about continuous
counting mode operation.
Publication Release Date: June 14, 2011
Revision V2.01