NUC130RE3CN Nuvoton Technology Corporation of America, NUC130RE3CN Datasheet - Page 309

• Manufacturer Part Number: NUC130RE3CN
• Description: IC MCU 32BIT 128KB FLASH 64LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130RE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.10.4 Function Description
5.10.4.1 One –Shot Mode
5.10.4.2 Periodic Mode
5.10.4.3 Toggle Mode
Timer controller provides one-shot, period, toggle and continuous counting operation modes. It
also provides the event counting function to count the event from external pin and input capture
function to capture or reset timer counter value. Each operating function mode is shown as
following:
If timer is operated at one-shot mode and CEN (TCSR[30] timer enable bit) is set to 1, the timer
counter starts up counting. Once the timer counter value reaches timer compare register
(TCMPR) value, if IE (TCSR[29] interrupt enable bit) is set to 1, then the timer interrupt flag is set
and the interrupt signal is generated and sent to NVIC to inform CPU. It indicates that the timer
counting overflow happens. If IE (TCSR[29] interrupt enable bit) is set to 0, no interrupt signal is
generated. In this operating mode, once the timer counter value reaches timer compare register
(TCMPR) value, the timer counter value goes back to counting initial value and CEN (timer enable
bit) is cleared to 0 by timer controller. Timer counting operation stops, once the timer counter
value reaches timer compare register (TCMPR) value. That is to say, timer operates timer
counting and compares with TCMPR value function only one time after programming the timer
compare register (TCMPR) value and CEN (timer enable bit) is set to 1. So, this operating mode
is called One-Shot mode.
If timer is operated at period mode and CEN (TCSR[30] timer enable bit) is set to 1, the timer
counter starts up counting. Once the timer counter value reaches timer compare register
(TCMPR) value, if IE (TCSR[29] interrupt enable bit) is set to 1, then the timer interrupt flag is set
and the interrupt signal is generated and sent to NVIC to inform CPU. It indicates that the timer
counting overflow happens. If IE (TCSR[29] interrupt enable bit) is set to 0, no interrupt signal is
generated. In this operating mode, once the timer counter value reaches timer compare register
(TCMPR) value, the timer counter value goes back to counting initial value and CEN is kept at 1
(counting enable continuously). The timer counter operates up counting again. If the interrupt flag
is cleared by software, once the timer counter value reaches timer compare register (TCMPR)
value and IE (interrupt enable bit) is set to 1’b1, then the timer interrupt flag is set and the
interrupt signal is generated and sent to NVIC to inform CPU again. That is to say, timer operates
timer counting and compares with TCMPR value function periodically. The timer counting
operation doesn’t stop until the CEN is set to 0.
periodically. So, this operating mode is called Periodic mode.
If timer is operated at toggle mode and CEN (TCSR[30] timer enable bit) is set to 1, the timer
counter starts up counting. Once the timer counter value reaches timer compare register
(TCMPR) value, if IE (TCSR[29] interrupt enable bit) is set to 1, then the timer interrupt flag is set
and the interrupt signal is generated and sent to NVIC to inform CPU. It indicates that the timer
counting overflow happens. The associated toggle output (tout) signal is set to 1. In this operating
mode, once the timer counter value reaches timer compare register (TCMPR) value, the timer
counter value goes back to counting initial value and CEN is kept at 1 (counting enable
continuously). The timer counter operates up counting again. If the interrupt flag is cleared by
software, once the timer counter value reaches timer compare register (TCMPR) value and IE
(interrupt enable bit) is set to 1, then the timer interrupt flag is set and the interrupt signal is
generated and sent to NVIC to inform CPU again. The associated toggle output (tout) signal is set
to 0. The timer counting operation doesn’t stop until the CEN is set to 0. Thus, the toggle output
(tout) signal is changing back and forth with 50% duty cycle. So, this operating mode is called
Toggle mode.
NuMicro™ NUC130/NUC140 Technical Reference Manual
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The interrupt signal is also generated
Publication Release Date: June 14, 2011
Revision V2.01