NUC130RE3CN Nuvoton Technology Corporation of America, NUC130RE3CN Datasheet - Page 296

• Manufacturer Part Number: NUC130RE3CN
• Description: IC MCU 32BIT 128KB FLASH 64LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130RE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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NuMicro™ NUC130/NUC140 Technical Reference Manual
TX_NUM
TX_BIT_LEN
TX_NEG
RX_NEG
GO_BUSY
0 = The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1
Numbers of Transmit/Receive Word
This field specifies how many transmit/receive word numbers should be executed in
one transfer.
00 = Only one transmit/receive word will be executed in one transfer.
01 = Two successive transmit/receive words will be executed in one transfer. (burst
10 = Reserved.
11 = Reserved.
Note: in slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave
Transmit Bit Length
This field specifies how many bits are transmitted in one transaction. Up to 32 bits can
be transmitted.
TX_BIT_LEN = 0x01 … 1 bit
TX_BIT_LEN = 0x02 … 2 bits
……
TX_BIT_LEN = 0x1F … 31 bits
TX_BIT_LEN = 0x00 … 32 bits
Transmit At Negative Edge
1 = The transmitted data output signal is changed at the falling edge of SPICLK
0 = The transmitted data output signal is changed at the rising edge of SPICLK
Receive At Negative Edge
1 = The received data input signal is latched at the falling edge of SPICLK
0 = The received data input signal is latched at the rising edge of SPICLK
Go and Busy Status
1 = In master mode, writing 1 to this bit to start the SPI data transfer; in slave mode,
0 = Writing 0 to this bit to stop data transfer if SPI is transferring.
During the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit
will be cleared automatically.
Note:
1.
2.
the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1).
register that is depends on the TX_BIT_LEN field).
writing 1 to this bit indicates that the slave is ready to communicate with a master.
mode)
All registers should be set before writing 1 to this GO_BUSY bit.
In FIFO mode, this bit will be controlled by hardware. Software should not modify
this bit.
select pin must be kept at active state during the successive data transfer.
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Publication Release Date: June 14, 2011
Revision V2.01