P80C592FFA/00,518 NXP Semiconductors, P80C592FFA/00,518 Datasheet - Page 52
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P80C592FFA/00,518
Manufacturer Part Number
P80C592FFA/00,518
Description
IC 80C51 MCU 8BIT ROMLESS 68PLCC
Manufacturer
NXP Semiconductors
Series
80Cr
Datasheet
1.P80C592FFA00512.pdf
(108 pages)
Specifications of P80C592FFA/00,518
Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-LCC (J-Lead)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P80C592FFA/00,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
13.5.19.2 Time Segment 1 (TSEG1)
This segment determines the location of the sampling
point within a bit period, which is at the end of TSEG1.
TSEG1 is programmable from 1 to 16 system clock cycles
(see Section 13.5.10).
The correct location of the sample point is essential for the
correct functioning of a transmission. The following points
must be taken into consideration:
1996 Jun 27
handbook, full pagewidth
A Start-Of-Frame (see Section 13.6.2) causes all
CAN-controllers to perform a ‘hard synchronization’
(see Section 13.5.20) on the first recessive-to-dominant
edge.
During arbitration, however, several CAN-controllers
may simultaneously transmit. Therefore it may require
twice the sum of bus-line, input comparator and the
output driver delay times until the bus is stable.
This is the propagation delay time.
8-bit microcontroller with on-chip CAN
(a) As defined by the CAN-protocol.
(b) As implemented in the P8xC592's on-chip CAN-controller.
transmit point
1 clock cycle (t
SYNC.SEG
t SYNCSEG
SCL
)
PROP.SEG
Fig.18 Bit period.
t TSEG1
nominal bit time
t (one bit period)
52
PHASE SEG1
(a)
(b)
To avoid sampling at an incorrect position, it is
necessary to include an additional synchronization
buffer on both sides of the sample point.
The main reasons for incorrect sampling are:
– Incorrect synchronization due to spikes on the
– Slight variations in the oscillator frequency of each
Time Segment 1 consists of the segment for
compensation of propagation delays and the
synchronization buffer segment directly before the
sample point (see Fig.18).
bus-line
CAN-controller in the network, which results in a
phase error.
sample point
sample point
PHASE SEG2
t TSEG2
MGA163
Product specification
P8xC592