P80C592FFA/00,518 NXP Semiconductors, P80C592FFA/00,518 Datasheet - Page 41
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P80C592FFA/00,518
Manufacturer Part Number
P80C592FFA/00,518
Description
IC 80C51 MCU 8BIT ROMLESS 68PLCC
Manufacturer
NXP Semiconductors
Series
80Cr
Datasheet
1.P80C592FFA00512.pdf
(108 pages)
Specifications of P80C592FFA/00,518
Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-LCC (J-Lead)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P80C592FFA/00,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
13.5.7
The Acceptance Code Register is part of the acceptance
filter of the CAN-controller. This register can be accessed
(read/write), if the Reset Request bit is set HIGH (present).
When a message is received which passes the
acceptance test and if there is an empty Receive Buffer,
then the respective Descriptor and Data Field
(see Fig.15) are sequentially stored in this empty buffer.
In the event that there is no empty Receive Buffer, the
Data Overrun bit is set HIGH (overrun); see
Sections 13.5.5 and 13.5.6.
Table 41 Acceptance Code Register (address 4)
Table 42 Description of the ACR bits
13.5.8
The Acceptance Mask Register is part of the acceptance
filter of the CAN-controller.
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).
Table 43 Acceptance Mask Register (address 5)
Table 44 Description of the AMR bits
1996 Jun 27
BIT
BIT
8-bit microcontroller with on-chip CAN
to
to
7
0
7
0
AM.7
AC.7
7
7
AC.7
to
AC.0
AM.7
to
AM.0
A
A
SYMBOL
CCEPTANCE
CCEPTANCE
SYMBOL
AM.6
AC.6
6
6
C
M
Acceptance Code. The Acceptance Code bits (AC.7 to AC.0) and the eight most significant
bits of the message's Identifier (ID.10 to ID.3) must be equal to those bit positions which are
marked relevant by the Acceptance Mask bits (AM.7 to AM.0).
The acceptance is given, if the following equation is satisfied:
(ID10 ... ID.3) = [(AC.7 ... AC.0) or (AM.7 ... AM.0)] = 1111 1111 B.
ODE
Acceptance Mask. If the Acceptance Mask bit is:
ASK
HIGH (don’t care), then this bit position is ‘don’t care’ for the acceptance of a message.
LOW (relevant), then this bit position is ‘relevant’ for acceptance filtering.
R
R
EGISTER
EGISTER
AM.5
AC.5
5
5
(AMR)
(ACR)
AM.4
AC.4
4
4
41
When the complete message has been correctly received
the following occurs:
During transmission of a message which passes the
acceptance test, the message is also written to its own
Receive Buffer. If no Receiver Buffer is available, Data
Overrun is signalled because it is not known at the start of
a message whether the CAN-controller will lose arbitration
and so become a receiver of the message.
The Acceptance Mask Register qualifies which of the
corresponding bits of the acceptance code are ‘relevant’ or
‘don't care’ for acceptance filtering.
The Receive Buffer Status bit is set HIGH (full)
If the Receive Interrupt Enable bit is set HIGH (enabled),
the Receive Interrupt is set HIGH (set).
AM.3
AC.3
FUNCTION
FUNCTION
3
3
AM.2
AC.2
2
2
AM.1
AC.1
1
1
Product specification
P8xC592
AM.0
AC.0
0
0