P80C557E4EFB/01,51 NXP Semiconductors, P80C557E4EFB/01,51 Datasheet - Page 32
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P80C557E4EFB/01,51
Manufacturer Part Number
P80C557E4EFB/01,51
Description
IC 80C51 MCU 1024 ROMLESS 80QFP
Manufacturer
NXP Semiconductors
Series
80Cr
Datasheet
1.P80C557E4EFB0155.pdf
(72 pages)
Specifications of P80C557E4EFB/01,51
Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
40
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-BQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P80C557E4EFB/01,51
Manufacturer:
SILICON
Quantity:
459
Company:
Part Number:
P80C557E4EFB/01,51
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
The Control Register, S1CON:
The CPU can read from and write to this 8-bit, directly addressable
SFR. Two bits are affected by the SIO1 hardware: the SI bit is set
when a serial interrupt is requested, and the STO bit is cleared when
a STOP condition is present on the I
cleared when ENS1 = 0.
Table 24. Description of S1CON bits
1999 Mar 02
Single-chip 8-bit microcontroller
SYMBOL
ENS1
STO
CR2
STA
CR1
CR0
AA
SI
S1CON (D8H)
S1CON.7
S1CON.6
S1CON.5
S1CON.4
S1CON.3
S1CON.2
S1CON.1
S1CON.0
BIT
CR2
Clock rate bit 2, see Table 25.
ENS1 = 0:
ENS1 = 1:
START flag. When this bit is set in slave mode, the hardware checks the I
condition if the bus is free or after the bus becomes free. If the device operates in master mode it will
generate a repeated START condition.
STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on
the I
condition. In this case no STOP condition is generated to the I
and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware.
Serial Interrupt flag. This flag is set, and an interrupt request is generated, after any of the following events
occur:
– A START condition is generated in master mode.
– The own slave address has been received during AA = 1.
– The general call address has been received while S1ADR.0 and AA = 1.
– A data byte has been received or transmitted in master mode (even if arbitration is lost).
– A data byte has been received or transmitted as selected slave.
– A STOP or START condition is received as selected slave receiver or transmitter.
While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset by software.
Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following
conditions:
– Own slave address is received.
– General call address is received (S1ADR.0 = 1).
– A data byte is received, while the device is programmed to be a master receiver.
– A data byte is received. while the device is a selected slave receiver.
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own
address or general call address is received.
Clock rate bits 1 and 0, see Table 25.
2
7
C bus. The STO bit is also
2
C bus clears this bit. This bit may also be set in slave mode in order to recover from an error
ENS1
6
Figure 30. Serial control (S1CON) register.
Serial I/O
Serial I/O
STA
5
disabled and reset. SDA and SCL outputs are high-Z.
enabled.
32
STO
4
P83C557E4/P80C557E4/P89C557E4
FUNCTION
SI
3
2
C bus, but the hardware releases the SDA
AA
2
2
C bus and generates a START
CR1
1
Product specification
CR0
0