P80C557E4EFB/01,51 NXP Semiconductors, P80C557E4EFB/01,51 Datasheet - Page 27

• Manufacturer Part Number: P80C557E4EFB/01,51
• Description: IC 80C51 MCU 1024 ROMLESS 80QFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C557E4EFB/01,51

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-BQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 20. Description of STE bits
Table 21. Description of RTE bits
For more information concerning the TM2CON, CTCON, TM2IR and
the STE/RTE registers see IC20 handbook, chapter “80C51 family
hardware description”.
Port 4 can be read and written by software without affecting the
toggle, set and reset signals. At a byte overflow of the least
1999 Mar 02
Single-chip 8-bit microcontroller
SYMBOL
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
SYMBOL
RTE (EFH)
STE (EEH)
RP45
RP44
RP43
RP42
RP41
RP40
TP47
TP46
STE.7
STE.6
STE.5
STE.4
STE.3
STE.2
STE.1
STE.0
BIT
TP47
TG47
FUNCTION
If “1” then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle
If “1” then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle
If “1” then P4.5 is set on a match between CM0 and Timer T2
If “1” then P4.4 is set on a match between CM0 and Timer T2
If “1” then P4.3 is set on a match between CM0 and Timer T2
If “1” then P4.2 is set on a match between CM0 and Timer T2
If “1” then P4.1 is set on a match between CM0 and Timer T2
If “1” then P4.0 is set on a match between CM0 and Timer T2
RTE.7
RTE.6
RTE.5
RTE.4
RTE.3
RTE.2
RTE.1
RTE.0
7
7
BIT
TP46
TG46
Figure 26. Reset/Toggle enable register (RTE).
6
6
Figure 25. Set enable register (STE).
FUNCTION
If “1” then P4.7 toggles on a match between CM2 and Timer T2
If “1” then P4.6 toggles on a match between CM2 and Timer T2
If “1” then P4.5 toggles on a match between CM1 and Timer T2
If “1” then P4.4 toggles on a match between CM1 and Timer T2
If “1” then P4.3 toggles on a match between CM1 and Timer T2
If “1” then P4.2 toggles on a match between CM1 and Timer T2
If “1” then P4.1 toggles on a match between CM1 and Timer T2
If “1” then P4.0 toggles on a match between CM1 and Timer T2
RP45
SP45
5
5
27
RP44
SP44
4
4
P83C557E4/P80C557E4/P89C557E4
significant byte, or at a 16-bit overflow of the timer/counter, an
interrupt sharing the same interrupt vector is requested. Either one
or both of these overflows can be programmed to request an
interrupt.
All interrupt flags must be reset by software.
RP43
SP43
3
3
RP42
SP42
2
2
RP41
SP41
1
1
Product specification
RP40
SP40
0
0