LPC1853FET256,551 NXP Semiconductors, LPC1853FET256,551 Datasheet - Page 41
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LPC1853FET256,551
Manufacturer Part Number
LPC1853FET256,551
Description
IC MCU 32BIT 512KB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1853FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NXP Semiconductors
LPC1850_30_20_10
Objective data sheet
7.12.6.1 Features
7.12.7.1 Features
7.12.6 High-speed USB Host/Device/OTG interface (USB0)
7.12.7 High-speed USB Host/Device interface with ULPI (USB1)
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
Remark: USB0 is not available on the LPC1810 (see
The USB OTG module allows the part to connect directly to a USB host such as a PC (in
device mode) or to a USB device in host mode.
Remark: USB1 is not available on the LPC1820/10 (see
The USB1 interface can operate as a full-speed USB host/device interface or can connect
to an external ULPI PHY for High-speed operation.
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Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, 16, or 32 data bits per device.
Separate reset domains allow the for auto-refresh through a chip reset if desired.
Complies with Universal Serial Bus specification 2.0.
Complies with USB On-The-Go supplement.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals.
Supports all full-speed USB-compliant peripherals.
Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
Contains UTMI+ compliant transceiver (PHY).
Supports interrupts.
This module has its own, integrated DMA engine.
Complies with Universal Serial Bus specification 2.0.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals if connected to external ULPI
PHY.
Supports all full-speed USB-compliant peripherals.
Supports interrupts.
This module has its own, integrated DMA engine.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 17 February 2011
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
Table
Table
2).
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© NXP B.V. 2011. All rights reserved.
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