LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 22
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NXP Semiconductors
Table 3.
LPC1850_30_20_10
Objective data sheet
Symbol
PD_5
PD_6
PD_7
PD_8
PD_9
PD_10
PD_11
PD_12
PD_13
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Pin description
P6
R6
T6
P8
T11
P11
N9
N11
T14
…continued
Reset
state
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
Type Description
-
O
I/O
-
-
O
I/O
-
-
I
I/O
-
-
I
I/O
-
-
O
I/O
-
-
I
O
-
-
-
O
-
-
-
O
-
-
I
O
-
All information provided in this document is subject to legal disclaimers.
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CTOUT_9 — SCT output 9. Match output 1 of timer 2.
EXTBUS_D19 — External memory data line 19.
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CTOUT_10 — SCT output 10. Match output 2 of timer 2.
EXTBUS_D20 — External memory data line 20.
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CTIN_5 — SCT input 5. Capture input 2 of timer 2.
EXTBUS_D21 — External memory data line 21.
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CTIN_6 — SCT input 6. Capture input 1 of timer 3.
EXTBUS_D22 — External memory data line 22.
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CTOUT_13 — SCT output 13. Match output 1 of timer 3.
EXTBUS_D23 — External memory data line 23.
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CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2.
EXTBUS_BLS3 — LOW active Byte Lane select signal 3.
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EXTBUS_CS3 — LOW active Chip Select 3 signal.
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EXTBUS_CS2 — LOW active Chip Select 2 signal.
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CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.
EXTBUS_BLS2 — LOW active Byte Lane select signal 2.
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Rev. 1.2 — 17 February 2011
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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