PIC18F1320-H/P Microchip Technology, PIC18F1320-H/P Datasheet - Page 31

• Manufacturer Part Number: PIC18F1320-H/P
• Description: IC MCU 8BIT 8KB FLASH 18PDIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-H/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-3:
© 2007 Microchip Technology Inc.
Primary System
Clock
(PRI_IDLE mode)
T1OSC or
INTRC
INTOSC
Sleep mode
Note 1:
Clock in Power
Managed Mode
2:
3:
4:
5:
(1)
(2)
In this instance, refers specifically to the INTRC clock source.
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
Two-Speed Start-up is covered in greater detail in Section 19.3 “Two-Speed Start-up”.
Execution continues during the INTOSC stabilization period.
Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
EC, RC, INTRC
EC, RC, INTRC
EC, RC, INTRC
EC, RC, INTRC
Primary System
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
HSPLL
HSPLL
HSPLL
HSPLL
Clock
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
OST + 2 ms
OST + 2 ms
OST + 2 ms
Mode Exit
Managed
5-10 μs
5-10 μs
5-10 μs
5-10 μs
1 ms
1 ms
Power
Delay
None
OST
OST
OST
(4)
(4)
(5)
(5)
(5)
(5)
Clock Ready
(OSCCON)
Status Bit
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
—
—
—
—
CPU and peripherals
clocked by primary
clock and executing
instructions.
CPU and peripherals
clocked by selected
power managed mode
clock and executing
instructions until
primary clock source
becomes ready.
Not clocked or
Two-Speed Start-up (if
enabled) until primary
clock source becomes
ready
PIC18F1220/1320
Exit by Interrupt
(3)
Activity during Wake-up from
.
Power Managed Mode
Not clocked or
Two-Speed Start-up
(if enabled)
Exit by Reset
DS39605F-page 29
(3)
.