PIC18F1320-H/P Microchip Technology, PIC18F1320-H/P Datasheet - Page 190
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PIC18F1320-H/P
Manufacturer Part Number
PIC18F1320-H/P
Description
IC MCU 8BIT 8KB FLASH 18PDIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1320-H/P
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
18-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F1220/1320
19.5.2
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM,
regardless of the protection bit settings.
19.5.3
The configuration registers can be write-protected. The
WRTC bit controls protection of the configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
19.6
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions,
or during program/verify. The ID locations can be read
when the device is code-protected.
19.7
PIC18F1220/1320 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed (see Table 19-4).
DS39605F-page 188
Note:
ID Locations
In-Circuit Serial Programming
DATA EEPROM
CODE PROTECTION
CONFIGURATION REGISTER
PROTECTION
The Timer1 oscillator shares the T1OSI
and T1OSO pins with the PGD and PGC
pins
debugging.
When using the Timer1 oscillator, In-Circuit
Serial Programming (ICSP) may not
function correctly (high voltage or low
voltage), or the In-Circuit Debugger (ICD)
may not communicate with the controller.
As a result of using either ICSP or ICD, the
Timer1 crystal may be damaged.
If ICSP or ICD operations are required, the
crystal should be disconnected from the
circuit (disconnect either lead), or installed
after programming. The oscillator loading
capacitors may remain in-circuit during
ICSP or ICD operation.
used
for
programming
and
TABLE 19-4:
19.8
When the DEBUG bit in configuration register,
CONFIG4L, is programmed to a ‘0’, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB
IDE. When the microcontroller has this feature
enabled, some resources are not available for general
use. Table 19-5 shows which resources are required by
the background debugger.
TABLE 19-5:
To use the In-Circuit Debugger function of the
microcontroller, the design must implement In-Circuit
Serial Programming connections to MCLR/V
V
Debugger module available from Microchip, or one of the
third party development tool companies (see the note fol-
lowing Section 19.7 “In-Circuit Serial Programming”
for more information).
Signal
MCLR
I/O pins:
Stack:
Program Memory:
Data Memory:
PGM
SS
PGD
PGC
V
V
DD
SS
, RB7 and RB6. This will interface to the In-Circuit
RB6/PGC/T1OSO/
In-Circuit Debugger
T13CKI/P1C/KBI2
RB7/PGD/T1OSI/
MCLR/V
RB5/PGM/KBI1
P1D/KBI3
V
V
Pin
DD
SS
PP
ICSP/ICD CONNECTIONS
DEBUGGER RESOURCES
/RA5
© 2007 Microchip Technology Inc.
Shared with T1OSC – protect
crystal
Shared with T1OSC – protect
crystal
Optional – pull RB5 low is
LVP enabled
RB6, RB7
512 bytes
10 bytes
2 levels
Notes
PP
, V
DD
®
,
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