PIC18F1320-H/P Microchip Technology, PIC18F1320-H/P Datasheet - Page 154

• Manufacturer Part Number: PIC18F1320-H/P
• Description: IC MCU 8BIT 8KB FLASH 18PDIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-H/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F1220/1320
16.5
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the RB1/AN5/TX/CK/INT1 pin
(instead of being supplied internally in Master mode).
This allows the device to transfer or receive data while
in any low-power mode.
16.5.1
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 16-9:
DS39605F-page 152
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
Legend: x = unknown
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREG
register.
Flag bit, TXIF, will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit, TXIF, will now be
set.
If enable bit, TXIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
EUSART Synchronous
Slave Mode
EUSART Transmit Register
Baud Rate Generator Register High Byte
Baud Rate Generator Register Low Byte
EUSART SYNCHRONOUS
SLAVE TRANSMIT
GIE/GIEH
SPEN
CSRC
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
, –
PEIE/GIEL
= unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
INT0IE
CREN
SYNC
SCKP
Bit 4
TXIF
TXIE
TXIP
ADDEN
SENDB
BRG16
RBIE
Bit 3
—
—
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
BRGH
FERR
Bit 2
—
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
RBIF
Bit 0
© 2007 Microchip Technology Inc.
0000 000x
-000 -000
-000 -000
-111 -111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
POR, BOR
Value on
0000 000u
-000 -000
-000 -000
-111 -111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
Value on
all other
Resets