ST52T440F3M6 STMicroelectronics, ST52T440F3M6 Datasheet - Page 44

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ST52T440F3M6

Manufacturer Part Number
ST52T440F3M6
Description
MCU 8-Bit ST52 CISC 8KB EPROM 5V 20-Pin SO
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST52T440F3M6

Package
20SO
Family Name
ST52
Maximum Speed
20 MHz
Ram Size
256 Byte
Program Memory Size
8 KB
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Program Memory Type
EPROM
Number Of Programmable I/os
13
On-chip Adc
6-chx12-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
1

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ST52T400/T440/E440/T441
5.2.4 Brown-Out Detector (BOD).
The on-chip Brown-Out Detector circuit prevents
the processor from falling into an unpredictable
state if the power supply drops below a certain
level.
When Vdd drops below the Brown-out detection
level, the Brown-out causes an internal proces-
sor reset RST that remains active as long as Vdd
remains below the Brown-Out Trigger Level.
Brown-Out resets the entire device except the
Power-on Detector and the Brown-out itself.
Enabling/disabling the Brown-out detector can be
performed by setting the software of the control bit
BOD of REG_CONF0 (Table 4.1).
When Vdd increases above the Trigger Level, the
Brown-Out reset is turned off after a delay of 4096
CPU clock cycles, which ensures stabilization of
the oscillator.
The Brown-Out falling voltage level typical value is
3.8V and the corresponding rising voltage activa-
tion level is 4.1V.
A minimum hysteresis of 250mV for the trigger is
guaranteed for spike free brown-out detection.
Brown-Out circuit detects a drop if Vdd voltage
stays below the safe threshold for longer than 100
Clock cycles before activation/deactivation of the
Brown-Out in order to filter voltage spikes.
Brown-Out function is disabled by default and is
not active when in HALT mode.
Remark: for higher frequencies, the device needs
Supply Voltage higher than the BOD threshold.
For this reason the BOD cannot work in this range
of frequencies. See Electrical Characteristic
Chapter in this Datasheet.
5.3 Power Saving Modes
There are two Power Saving modes: WAIT and
HALT mode. These conditions may be entered by
using the WAIT and HALT instructions.
5.3.1 Wait Mode.
Wait mode places the MCU in a low power con-
sumption by stopping the CPU. All peripherals and
the watchdog remain active. During WAIT mode,
the Interrupts are enabled. The MCU will remain in
Wait mode until an Interrupt or a RESET occurs,
whereupon the Program jumps to the interrupt
service routine or, if a RESET occurs, at the
beginning of the user program.
Remark: in Wait mode the CPU clock does’t stop.
44/94
5.3.2 Halt Mode.
Halt mode is the MCU’s lowest power consump-
tion mode, which is entered by executing the
HALT instruction. The internal oscillator is turned
off, causing all internal processing to be stopped,
including the operations of the on-chip peripher-
als.
Halt mode cannot be used when the watchdog
is enabled. If the HALT instruction is executed
while the watchdog system is enabled, it will be
skipped without modifying the normal CPU opera-
tions.
The ICU can exit Halt mode after an external inter-
rupt or reset. The oscillator is then turned on and
stabilization time is provided before restarting
CPU operations. Stabilization time is 4096 CPU
clock cycles after the interrupt and 1.000.000 after
the Reset.
After the start up delay, the CPU restarts opera-
tions by serving the external interrupt routine.
Reset makes the ICU exit from HALT mode and
restart, after the delay, from the beginning of the
user program after the delay.
Warning: if the External Interrupt is disabled, the
ICU exits from the Halt mode and jumps to the
lower priority interrupt routine.
Figure 5.3 WAIT Flow Chart

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