ST52T440F3M6 STMicroelectronics, ST52T440F3M6 Datasheet - Page 43

• Manufacturer Part Number: ST52T440F3M6
• Description: MCU 8-Bit ST52 CISC 8KB EPROM 5V 20-Pin SO
• Manufacturer: STMicroelectronics

Specifications of ST52T440F3M6

• Package: 20SO
• Family Name: ST52
• Maximum Speed: 20 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 13
• On-chip Adc: 6-chx12-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 1

5.2 Reset
There are four sources of Reset:
- RESET pin (external source)
- WATCHDOG (internal source)
- POWER ON Reset (Internal source)
- BROWN OUT Reset (Internal source)
When a Reset event happens, all the registers are
set to the reset value and the user program
restarts from the beginning.
5.2.1 External Reset.
The Reset pin is an input pin. An internal reset
does not affect this pin.
A Reset signal originated by external sources is
recognized istantaneously. The RESET pin may
be used to ensure Vdd has risen to a point where
the MCU can operate correctly before the user
program is run. In working mode the Reset must
be set to ‘1’ (see Table 1.1)
5.2.2 Reset Operation.
The duration of a RESET condition is fixed at
1.000.000 internal CPU clock cycles (or 4096 in
case of BOD).
Following a Power-On Reset event, or after exit-
ing Halt Mode, a 1.000.000 CPU clock cycle delay
period is initiated in order to allow the oscillator to
stabilize and to ensure that recovery has taken
place from the Reset state.
A Pull up resistor of 100 K
RESET pin is at level “1” when no HALT or
Power-On events occurred.
Figure 5.2 Reset Block Diagram
RESET
Vdd
POWER-ON
RESET
guarantees that
Vdd
Vdd
BROWN-
OUT
If an external resistor is connected to the RESET
pin a minimum value of 10K
After a RESET procedure is completed, the core
reads the instruction stored in the first 3 bytes of
the EPROM, which contains a JUMP instruction to
the EPROM address containing the first instruc-
tion of the user program. The Assembler tool auto-
matically generates this Jump instruction with the
first instruction address.
5.2.3 Power-on Reset (POR).
A Power-On Reset is generated by an on-chip
detection circuit. This circuit ensures that the
device is not started until Vdd has reached the
nominal level of 2.3V and allows the clock oscilla-
tor to stabilize.
Once 2.3V are reached, the Power-On circuit gen-
erates an internal RST signal that releases the
internal reset to the CPU and invokes a delay
counter of 1.000.000 CPU clock cycles, during
which the device is kept in RESET after Vdd has
risen.
A correct operation of Power-on detector is guar-
anteed if the slew rate of Vdd is 0.05 V/ms.
Note: The power supply must fall below 0 V for
the internal POR circuit to detect the next rise of
Vdd.
At power on the POR is enabled by default.
POR is designed exclusively to cope with power-
up conditions and should not be used to detect a
drop in the power supply voltage, for which the
Brown-out Detector can be used instead.
WATCHDOG
COUNTER x
COUNTER x
1.000.000
4096
WATCHDOG RESET
BROWN-OUT RESET
ST52T400/T440/E440/T441
INTERNAL RESET
must be used.
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