XC5204-3PQ160C Xilinx Inc, XC5204-3PQ160C Datasheet - Page 36

• Manufacturer Part Number: XC5204-3PQ160C
• Description: FPGA XC5200 Family 6K Gates 480 Cells 83MHz 0.5um (CMOS) Technology 5V 160-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC5204-3PQ160C

• Package: 160PQFP
• Family Name: XC5200
• Device Logic Units: 120
• Device System Gates: 6000
• Number Of Registers: 480
• Maximum Internal Frequency: 83 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 124
• Re-programmability Support: Yes

XC5200 Series Field Programmable Gate Arrays
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first byte of parallel configura-
tion data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con-
secutive rising CCLK edge.
The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
7-118
Figure 33: Synchronous Peripheral Mode Circuit Diagram
CONTROL
SIGNALS
DATA BUS
PROGRAM
CLOCK
3.3 k
Product Obsolete or Under Obsolescence
4.7 k
8
V
CC
RDY/BUSY
D
INIT
PROGRAM
CCLK
PERIPHERAL
0-7
M0 M1
SYNCHRO-
N/C
XC5200
NOUS
DONE
DOUT
M2
NOTE:
M2 can be shorted to Ground
if not used as I/O
3.3 k
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
The lead FPGA serializes the data and presents the pre-
amble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK peri-
ods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each
daisy-chained device.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, M0).
OPTIONAL
DAISY-CHAINED
FPGAs
INIT
CCLK
DIN
PROGRAM
M0 M1
XC5200E/EX
November 5, 1998 (Version 5.2)
SLAVE
N/C
DONE
DOUT
M2
X9005
R