XC5204-3PQ160C Xilinx Inc, XC5204-3PQ160C Datasheet - Page 34

• Manufacturer Part Number: XC5204-3PQ160C
• Description: FPGA XC5200 Family 6K Gates 480 Cells 83MHz 0.5um (CMOS) Technology 5V 160-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC5204-3PQ160C

• Package: 160PQFP
• Family Name: XC5200
• Device Logic Units: 120
• Device System Gates: 6000
• Number Of Registers: 480
• Maximum Internal Frequency: 83 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 124
• Re-programmability Support: Yes

XC5200 Series Field Programmable Gate Arrays
7-116
Figure 31: Master Parallel Mode Circuit Diagram
PROGRAM
NOTE:M0 can be shorted
to Ground if not used
as I/O.
4.7K
VCC
Product Obsolete or Under Obsolescence
3.3 K
DATA BUS
DOUT
PROGRAM
D7
D6
D5
D4
D3
D2
D1
D0
INIT
M0
XC5200
Parallel
Master
HIGH
LOW
M1
or
N/C
M2
DONE
CCLK
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
. . .
. . .
. . .
. . .
. . .
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
CE
TO DIN OF OPTIONAL
DAISY-CHAINED FPGAS
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
(OR LARGER)
EPROM
(8K x 8)
D7
D6
D5
D4
D3
D2
D1
D0
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN
ALTERNATIVE CONFIGURATIONS
November 5, 1998 (Version 5.2)
DONE
DIN
CCLK
PROGRAM
M0
XC4000E/EX/
XC5200/
Spartan
SLAVE
N/C
M1
M2
DOUT
INIT
X9004_01
R