ST24FC21M6TR STMicroelectronics, ST24FC21M6TR Datasheet - Page 16

• Manufacturer Part Number: ST24FC21M6TR
• Description: EEPROM Serial-I2C 1K-Bit 128 x 8 3.3V/5V 8-Pin SO N T/R
• Manufacturer: STMicroelectronics

Specifications of ST24FC21M6TR

• Package: 8SO N
• Interface Type: Serial-I2C
• Density: 1 Kb
• Maximum Operating Frequency: 0.1|0.4 MHz
• Maximum Random Access Time: 3500|900 ns
• Typical Operating Supply Voltage: 3.3|5 V
• Organization: 128x8
• Data Retention: 40 Year
• Hardware Data Protection: Yes
• Operating Temperature: -40 to 85 °C

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 12. Inhibited Write when VCLK/WC = 0
– Step 1: the Master issues a START condition
– Step 2: if the memory is busy with the internal
Read Operations
On delivery, the memory content is set at all "1’s"
(or FFh).
Current Address Read. The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends the Device Select code with the
RW bit set to ’1’. The memory acknowledges this
and outputs the data byte addressed by the internal
byte address counter. This counter is then incre-
mented. The master must NOT acknowledge the
data byte output and terminates the transfer with a
STOP condition.
16/22
followed by a Device Select byte (1st byte of
the new instruction).
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the mem-
ory is ready to receive the second part of the
instruction (the first byte of this instruction was
already sent during Step 1).
VCLK/WC
BYTE WRITE
PAGE WRITE
CONTROL
CONTROL
BYTE
BYTE
ACK
ACK
WORD ADD n
WORD ADDR
ACK
ACK
Random Address Read. A dummy write is per-
formed to load the address into the address
counter, see Figure 14. This is followed by a Re-
START condition send by the master and the De-
vice Select code is repeated with the RW bit set to
’1’. The memory acknowledges this and outputs the
addressed data byte. The master must NOT ac-
knowledge the data byte output and terminates the
transfer with a STOP condition.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last data byte
output, and MUST generate a STOP condition.
The output data is from consecutive byte ad-
dresses, with the internal byte address counter
automatically incremented after each byte output.
After a count of the last memory address, the
address counter will ’roll-over’ and the memory will
continue to output data.
Acknowledge in Read Mode. In all read modes
the ST24xy21 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
DATA n
DATA
ACK
ACK
DATA n + 1
ACK
DATA n + 7
ACK
AI01894