ST24FC21M6TR STMicroelectronics, ST24FC21M6TR Datasheet - Page 15

• Manufacturer Part Number: ST24FC21M6TR
• Description: EEPROM Serial-I2C 1K-Bit 128 x 8 3.3V/5V 8-Pin SO N T/R
• Manufacturer: STMicroelectronics

Specifications of ST24FC21M6TR

• Package: 8SO N
• Interface Type: Serial-I2C
• Density: 1 Kb
• Maximum Operating Frequency: 0.1|0.4 MHz
• Maximum Random Access Time: 3500|900 ns
• Typical Operating Supply Voltage: 3.3|5 V
• Organization: 128x8
• Data Retention: 40 Year
• Hardware Data Protection: Yes
• Operating Temperature: -40 to 85 °C

Figure 11. Write Modes Sequence
memory. The master then terminates the transfer
by generating a STOP condition.
Page Write. The Page Write mode allows up to 8
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the most significant memory ad-
dress bits are the same. The master sends from
one up to 8 bytes of data, which are each acknow-
ledged by the memory.
After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
VCLK/WC
BYTE WRITE
VCLK/WC
PAGE WRITE
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
ACK
DATA IN N
DEV SEL
DEV SEL
R/W
R/W
ACK
ACK
ACK
BYTE ADDR
BYTE ADDR
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master. The sequence is as follows:
– Initial condition: a Write is in progress (see Fig-
ure 10).
ACK
ACK
DATA IN 1
DATA IN
ACK
ACK
DATA IN 2
AI01893
W
) is given in the
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