MT90401AB Zarlink, MT90401AB Datasheet - Page 11

• Manufacturer Part Number: MT90401AB
• Description: Framer SDH/SONET 3.3V 80-Pin LQFP EP Tray
• Manufacturer: Zarlink

Specifications of MT90401AB

• Package: 80LQFP EP
• Number Of Transceivers: 1
• Standard Framing Format: SDH|SONET
• Maximum Supply Current: 150 mA
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V

The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL,
no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change
at the input of the DPLL, or at the output of the DPLL.
Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual
reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.
This phase error is a function of the difference in phase between the two input reference signals during reference
rearrangements. Each time a reference switch is made, the delay between input signal and output signal will
change. The value of this delay is the accumulation of the error measured during each reference switch.
The programmable delay circuit can be reset to zero by applying a logic low pulse to the TIE Circuit Clear (TCLR)
pin. A minimum reset pulse width is 300 ns. This results in a phase realignment between the input reference signal
and the output signal as shown in Figure 16. The speed of the phase alignment correction is limited to 885 ns/s in
SONET mode and 53 ns per 1.326 ms in SDH mode, convergence is in the direction of least phase travel.
The state diagram of Figure 12 indicates the state changes for which the TIE Corrector Circuit is activated.
from Reference
PRI or SEC
Select Mux
Programmable
Delay Circuit
Figure 3 - TIE Corrector Circuit
Zarlink Semiconductor Inc.
MT90401
TIE Corrector
State Machine
Control
Circuit
Enable
TCLR
from
11
Resets Delay
Delay Value
Control Signal
Select MUX
Signal from
Frequency
Compare
Feedback
Circuit
Reference to
Data Sheet
Virtual
DPLL