XC3190A-4PQ160C Xilinx Inc, XC3190A-4PQ160C Datasheet - Page 39

• Manufacturer Part Number: XC3190A-4PQ160C
• Description: FPGA XC3100A Family 6K Gates 320 Cells 227MHz CMOS Technology 5V 160-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC3190A-4PQ160C

• Package: 160PQFP
• Family Name: XC3100A
• Device Logic Units: 320
• Device System Gates: 6000
• Number Of Registers: 928
• Maximum Internal Frequency: 227 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 138
• Ram Bits: 64160
• Re-programmability Support: Yes
• Case: QFP160
• Dc: 98+

XC3000A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000A Operating Conditions
Note:
XC3000A DC Characteristics Over Operating Conditions
Notes:
November 9, 1998 (Version 3.1)
Symbol
Symbol
V
I
V
CCPD
I
V
V
V
V
V
V
V
V
I
CCPD
I
CCO
C
T
RLL
RIN
I
IHT
IHC
CC
ILT
ILC
OH
OH
OL
OL
IL
IN
IN
1. With no output current loads, no active input or Longline pull-up resistors, all package pins at V
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
3. Not tested. Allow an undriven pin to float High. For any other purposes use an external pull-up.
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C.
device configured with a tie option.
100 mA per V
R
Supply voltage relative to GND Commercial 0 C to +85 C junction
Supply voltage relative to GND Industrial -40 C to +100 C junction
High-level input voltage — TTL configuration
Low-level input voltage — TTL configuration
High-level input voltage — CMOS configuration
Low-level input voltage — CMOS configuration
Input signal transition time
High-level output voltage (@ I
Low-level output voltage (@ I
High-level output voltage (@ I
Low-level output voltage (@ I
Power-down supply voltage (PWRDWN must be Low)
Power-down supply current
Quiescent FPGA supply current in addition to I
Input Leakage Current
Input capacitance, all packages except PGA175
Input capacitance, PGA 175
Pad pull-up (when selected) @ V
Horizontal Longline pull-up (when selected) @ logic Low
(V
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
CC
CC(MAX)
pin. The number of ground pins varies from the XC3020A to the XC3090A.
@ T
MAX
)
Description
OL
OL
Description
OH
OH
= 4.0 mA, V
= 4.0 mA, V
= –4.0 mA, V
= –4.0 mA, V
IN
= 0 V
3
XC3000 Series Field Programmable Gate Arrays
CC
CC
CC
CC
CCPD
min)
min)
min)
min)
Commercial
Industrial
3020A
3030A
3042A
3064A
3090A
4.75
70%
Min
4.5
2.0
0
0
3.86
3.76
2.30
0.02
Min
–10
CC
or GND, and the FPGA
100%
5.25
20%
Max
V
250
5.5
0.8
Max
0.40
0.40
0.17
100
160
240
340
500
500
+10
3.4
CC
10
10
15
16
20
Units
Units
V
V
mA
mA
ns
pF
pF
pF
pF
V
V
V
V
CC
CC
V
V
V
V
V
A
A
A
A
A
A
A
A
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