XC3190A-4PQ160C Xilinx Inc, XC3190A-4PQ160C Datasheet - Page 13
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XC3190A-4PQ160C
Manufacturer Part Number
XC3190A-4PQ160C
Description
FPGA XC3100A Family 6K Gates 320 Cells 227MHz CMOS Technology 5V 160-Pin PQFP
Manufacturer
Xilinx Inc
Datasheet
1.XC3190A-4PQ160C.pdf
(76 pages)
Specifications of XC3190A-4PQ160C
Package
160PQFP
Family Name
XC3100A
Device Logic Units
320
Device System Gates
6000
Number Of Registers
928
Maximum Internal Frequency
227 MHz
Typical Operating Supply Voltage
5 V
Maximum Number Of User I/os
138
Ram Bits
64160
Re-programmability Support
Yes
Case
QFP160
Dc
98+
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Longlines
The Longlines bypass the switch matrices and are intended
primarily for signals that must travel a long distance, or
must have minimum skew among multiple destinations.
Longlines, shown in
tally the height or width of the interconnect area. Each inter-
connection column has three vertical Longlines, and each
interconnection row has two horizontal Longlines. Two
additional Longlines are located adjacent to the outer sets
of switching matrices. In devices larger than the XC3020A
and XC3120A FPGAs, two vertical Longlines in each col-
November 9, 1998 (Version 3.1)
Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.
R
Figure
14, run vertically and horizon-
XC3000 Series Field Programmable Gate Arrays
umn are connectable half-length lines. On the XC3020A
and XC3120A FPGAs, only the outer Longlines are con-
nectable half-length lines.
Longlines can be driven by a logic block or IOB output on a
column-by-column basis. This capability provides a com-
mon low skew control or clock line within each column of
logic blocks. Interconnections of these Longlines are
shown in
input to a Longline and are enabled automatically by the
development system when a connection is made.
Figure
15. Isolation buffers are provided at each
7-15
7