CY7C1019B-15VI Cypress Semiconductor Corp, CY7C1019B-15VI Datasheet - Page 4

• Manufacturer Part Number: CY7C1019B-15VI
• Description: SRAM Chip Async Single 5V 1M-Bit 128K x 8 15ns 32-Pin SOJ
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1019B-15VI

• Package: 32SOJ
• Timing Type: Asynchronous
• Density: 1 Mb
• Typical Operating Supply Voltage: 5 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 8 Bit
• Number Of Ports: 1
• Number Of Words: 128K

Data Retention Characteristics
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1
Read Cycle No. 2 (OE Controlled)
Notes:
Document #: 38-05026 Rev. *A
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
9.
V
I
t
t
Parameter
CCDR
CDR
R
DATA OUT
CURRENT
ADDRESS
DR
DATA OUT
ADDRESS
SUPPLY
Device is continuously selected. OE, CE = V
[3]
CE
V
V
OE
CE
CC
CC
V
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CC
[9, 10]
for Data Retention
PREVIOUS DATA VALID
HIGH IMPEDANCE
t
PU
Description
t
LZCE
[10, 11]
t
t
ACE
LZOE
IL
.
Over the Operating Range (L Version Only)
50%
t
OHA
t
t
DOE
CDR
3.0V
t
AA
t
RC
No input may exceed V
V
CE > V
V
DATA RETENTION MODE
CC
IN
> V
= V
t
RC
V
CC
CC
DR
DR
– 0.3V,
– 0.3V or V
> 2V
= 2.0V,
Conditions
DATA VALID
IN
CC
< 0.3V
+ 0.5V
t
HZOE
DATA VALID
3.0V
t
R
t
HZCE
Min.
t
200
2.0
PD
0
CY7C10191B
50%
CY7C1019B/
Max.
IMPEDANCE
300
HIGH
Page 4 of 9
Unit
ns
ICC
ISB
V
A
s