CY7C1019B-15VI Cypress Semiconductor Corp, CY7C1019B-15VI Datasheet - Page 3

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CY7C1019B-15VI

Manufacturer Part Number
CY7C1019B-15VI
Description
SRAM Chip Async Single 5V 1M-Bit 128K x 8 15ns 32-Pin SOJ
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1019B-15VI

Package
32SOJ
Timing Type
Asynchronous
Density
1 Mb
Typical Operating Supply Voltage
5 V
Address Bus Width
17 Bit
Number Of I/o Lines
8 Bit
Number Of Ports
1
Number Of Words
128K

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1019B-15VI
Manufacturer:
CYPRESS
Quantity:
25
AC Test Loads and Waveforms
Switching Characteristics
Document #: 38-05026 Rev. *A
OUTPUT
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes:
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
4.
5.
6.
7.
8.
Equivalent to:
Parameter
INCLUDING
JIG AND
SCOPE
5V
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
t
At any given temperature and voltage condition, t
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
OL
HZOE
/I
OH
OUTPUT
, t
HZCE
and 30-pF load capacitance.
30 pF
[7, 8]
, and t
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
(a)
HZWE
THÉ
R1 480
VENIN EQUIVALENT
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
167
Description
255
R2
[6]
[4]
[5, 6]
[6]
[5, 6]
[5, 6]
OUTPUT
Over the Operating Range
1.73V
INCLUDING
JIG AND
SCOPE
5V
HZCE
is less than t
5 pF
(b)
R1 480
LZCE
Min.
7C10191B-10
10
10
3
0
3
0
8
7
0
0
7
5
0
3
, t
HZOE
is less than t
255
R2
Max.
10
10
10
5
5
5
5
LZOE
GND
3.0V
, and t
HZWE
Min.
3 ns
12
12
7C1019B-12
3
0
3
0
9
8
0
0
8
6
0
3
HZWE
and t
is less than t
SD
.
Max.
12
12
12
10%
6
6
6
6
LZWE
90%
ALL INPUT PULSES
for any given device.
Min.
15
15
10
10
10
7C1019B-15
3
0
3
0
0
0
8
3
0
CY7C10191B
CY7C1019B/
Max.
15
15
15
7
7
7
7
Page 3 of 9
90%
10%
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3 ns

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