CY7C1019B-12ZC Cypress Semiconductor Corp, CY7C1019B-12ZC Datasheet

CY7C1019B-12ZC

Manufacturer Part Number
CY7C1019B-12ZC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1019B-12ZC

Density
1Mb
Access Time (max)
12ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
140mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 001-06425 Rev. **
Features
• High speed
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019
WE
— t
CE
OE
Logic Block Diagram
A
A
A
A
A
A
A
A
A
AA
0
1
2
3
4
5
6
7
8
= 12, 15 ns
INPUT BUFFER
512 x 256 x 8
DECODER
COLUMN
ARRAY
POWER
DOWN
198 Champion Court
Functional Description
The CY7C1019BN is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019BN is available in standard 32-pin TSOP Type
II and 400-mil-wide SOJ packages.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
0
San Jose
through I/O
,
128K x 8 Static RAM
I/O
I/O
V
V
I/O
I/O
WE
CA 95134-1709
CE
CC
A
A
A
A
A
A
A
A
SS
7
7
0
1
2
3
0
1
2
3
4
5
6
Pin Configurations
) is then written into the location
SOJ
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
Top View
0
0
through I/O
Revised February 1, 2006
through A
/ TSOPII
CY7C1019BN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
7
) are placed in a
).
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
408-943-2600
16
15
14
13
SS
CC
12
11
10
9
8
7
6
5
4
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Related parts for CY7C1019B-12ZC

CY7C1019B-12ZC Summary of contents

Page 1

... I/O pins. The eight input/output pins (I/O high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019BN is available in standard 32-pin TSOP Type II and 400-mil-wide SOJ packages. I/O 0 I/O 1 ...

Page 2

... Max mA, 140 OUT = 1 > MAX , CC – 0.3V – 0.3V, CC < 0.3V Test Conditions T = 25° MHz 5.0V CC CY7C1019BN 7C1019BN-15 Unit 15 ns 130 Ambient [2] Temperature ± 10% 0°C to +70°C 5V ± 10% –40°C to +85°C -15 Min. Max. Unit 2.4 V 0.4 0 0.3 2 ...

Page 3

... The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t Document #: 001-06425 Rev 480Ω 5V 3.0V R2 GND 5 pF 255Ω ≤ (b) -12 Min. Max less than less than t , and t HZCE LZCE HZOE LZOE and t HZWE CY7C1019BN ALL INPUT PULSES 90% 90% 10% 10% ≤ -15 Min. Max. Unit ...

Page 4

... Conditions No input may exceed 2.0V > V – 0.3V > V – 0. DATA RETENTION MODE 3.0V V > CDR OHA DOE DATA VALID 50% CY7C1019BN Min. Max. Unit + 0.5V 2 µA 300 < 0. µs 200 3. DATA VALID t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB Page [+] Feedback ...

Page 5

... If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied. Document #: 001-06425 Rev SCE SA t SCE PWE t SD DATA VALID [12, 13 SCE PWE t SD DATA VALID IN CY7C1019BN Page [+] Feedback ...

Page 6

... High Data Out Data High Z Ordering Information Speed (ns) Ordering Code 12 CY7C1019BN-12VC CY7C1019BN-12ZC CY7C1019BN-12ZXC 15 CY7C1019BN-15VC CY7C1019BN-15ZXC Please contact local sales representative regarding availability of these parts Document #: 001-06425 Rev. ** [13 SCE PWE t SD DATA VALID Mode 7 Power-Down Read Write Selected, Outputs Disabled Package Diagram ...

Page 7

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 32-pin TSOP II (51-85095) CY7C1019BN 51-85033-A 51-85033-*B ...

Page 8

... Document History Page Document Title: CY7C1019BN 128K x 8 Static RAM Document Number: 001-06425 REV. ECN NO. Issue Date ** 423847 See ECN Document #: 001-06425 Rev. ** Orig. of Change Description of Change NXR New Data Sheet CY7C1019BN Page [+] Feedback ...

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