CY7C1019B-12ZXC Cypress Semiconductor Corp, CY7C1019B-12ZXC Datasheet

IC SRAM 1MBIT 12NS 32TSOP

CY7C1019B-12ZXC

Manufacturer Part Number
CY7C1019B-12ZXC
Description
IC SRAM 1MBIT 12NS 32TSOP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1019B-12ZXC

Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
1M (128K x 8)
Speed
12ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
32-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Cypress Semiconductor Corporation
Document #: 38-05026 Rev. *B
Features
Functional Description
The CY7C1019B/10191B is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
WE
CE
OE
Logic Block Diagram
• High speed
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019
— t
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
AA
= 10, 12, 15 ns
INPUT BUFFER
512 x 256 x 8
DECODER
COLUMN
ARRAY
POWER
DOWN
198 Champion Court
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight
I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019B/10191B is available in standard 32-pin
TSOP Type II and 400-mil-wide SOJ packages. Customers
should use part number CY7C10191B when ordering parts
with 10 ns t
t
AA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
.
0
1
2
3
4
5
6
7
San Jose
AA
0
, and CY7C1019B when ordering 12 and 15 ns
through I/O
I/O
I/O
V
V
I/O
I/O
WE
CE
CC
A
A
A
A
A
A
A
A
SS
,
128K x 8 Static RAM
7
0
1
2
3
0
1
2
3
4
5
6
Pin Configurations
CA 95134-1709
SOJ
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
) is then written into the location
Top View
0
/ TSOPII
0
through I/O
Revised October 6, 2005
through A
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CY7C10191B
CY7C1019B
16
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
7
) are placed in a
16
15
14
13
SS
CC
12
11
10
9
8
).
7
6
5
4
408-943-2600

Related parts for CY7C1019B-12ZXC

CY7C1019B-12ZXC Summary of contents

Page 1

... HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019B/10191B is available in standard 32-pin TSOP Type II and 400-mil-wide SOJ packages. Customers should use part number CY7C10191B when ordering parts with and CY7C1019B when ordering 12 and I/O 0 ...

Page 2

... L V < MAX Max > V – 0.3V > V – 0.3V < 0.3V Test Conditions T = 25° MHz 5.0V CC CY7C1019B CY7C10191B 7C1019B- 140 130 Ambient [2] Temperature 0°C to +70°C –40°C to +85°C 7C1019B-12 7C1019B-15 Min. Max. Min. 2.4 2.4 0.4 2 0.3 – ...

Page 3

... The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t Document #: 38-05026 Rev 480Ω 255Ω INCLUDING JIG AND SCOPE (b) 1.73V Over the Operating Range 7C10191B-10 Min. Max less than less than t HZCE LZCE HZOE CY7C1019B CY7C10191B ALL INPUT PULSES 3.0V 90% 10% GND ≤ 7C1019B-12 7C1019B-15 Min. Max. Min ...

Page 4

... > V – 0.3V > V – 0. DATA RETENTION MODE 3.0V V > CDR OHA ACE t DOE t LZOE 50 CY7C1019B CY7C10191B Conditions Min. + 0.5V 2 < 0.3V IN 200 3. DATA VALID t HZOE t HZCE DATA VALID t PD 50% Max. Unit V μA 300 ns μs HIGH IMPEDANCE ICC ISB Page ...

Page 5

... If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05026 Rev SCE SCE PWE t SD DATA VALID [12, 13 SCE PWE t SD DATA VALID IN CY7C1019B CY7C10191B Page ...

Page 6

... X X High High Data Out Data High Z Ordering Information Speed (ns) Ordering Code 12 CY7C1019B-12VC CY7C1019B-12ZC CY7C1019B-12ZXC 15 CY7C1019B-15VC CY7C1019B-15VI CY7C1019B-15ZC CY7C1019B-15ZXC CY7C1019B-15ZI Please contact local sales representative regarding availability of parts Document #: 38-05026 Rev. *B [13 SCE PWE t HZWE –I/O Mode 0 7 Power-Down Power-Down Read ...

Page 7

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 32-Lead (400-mil) Molded SOJ V33 32-Lead TSOP II ZS32 CY7C1019B CY7C10191B 51-85033-A 51-85033-*B ...

Page 8

... Document History Page Document Title: CY7C1019B/CY7C10191B 128K x 8 Static RAM Document Number: 38-05026 REV. ECN NO. Issue Date ** 109949 09/25/01 *A 116170 08/14/02 *B 397875 See ECN Document #: 38-05026 Rev. *B Orig. of Change Description of Change SZV Change from Spec number: 38-01115 to 38-05026 HGK 1. SOJ (400-mil) package outline replacing incorrect SOJ package 2 ...

Related keywords