CS493253-CL Cirrus Logic Inc, CS493253-CL Datasheet - Page 45

• Manufacturer Part Number: CS493253-CL
• Description: Multi Standard Audio Decoder 44-Pin PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS493253-CL

• Package: 44PLCC
• Operating Temperature: 0 to 70 °C

4) The host should now terminate the read cycle
6.2.2. Motorola Parallel Host
The Motorola parallel host communication mode is
implemented using the pins given in
INTREQ pin is controlled by the application code
when a parallel host communication mode has been
selected. When the code supports INTREQ
notification, the INTREQ pin is asserted whenever
the DSP has an outgoing message for the host. This
same information is reflected by the HOUTRDY
bit of the Host Control Register (A[1:0] = 01b).
INTREQ is useful for informing the host of
unsolicited messages. An unsolicited message is
defined as a message generated by the DSP without
an associated host read request. Unsolicited
messages can be used to notify the host of
conditions such as a change in the incoming audio
data type (e.g. PCM --> AC-3)
6.2.2.1.Writing a Byte in Motorola Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
DS339PP4
Chip Select
Data Strobe
Read or Write Select
Register Address Bit 1
Register Address Bit 0
Interrupt Request
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
by driving the CS and RD pins high.
Table 7. Motorola Mode Communication Signals
Communication Mode
Mnemonic
CS
DS
R/W
A1
A0
INTREQ
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Pin Name
18
4
5
6
7
19
8
9
10
11
14
15
16
17
Table
Pin Number
7. The
must insure that all of the timing constraints of the
Motorola Parallel Host Mode Write Cycle are met.
The flow diagram shown in
the sequence of events that define a one-byte write
in Motorola mode. The protocol presented in
Figure 26
1) The host must drive the A1 and A0 register
2) The host initiates a write cycle by driving the
3) The host drives the data byte to the DATA[7:0]
4) Once the setup time for the write has been met,
Figure 26. Motorola Mode, One-Byte Write Flow
address pins of the CS493XX with the address
of the address of the desired Parallel I/O
Register.
Host Message:
Host Control:
PCMDATA:
CMPDATA:
The host indicates that this is a write cycle by
driving the R/W pin low.
CS and DS pins low.
pins of the CS493XX.
ADDRESS A PARALLEL I/O REGISTER
will now be described in detail.
(A[1:0] SET APPROPRIATELY
CS49300 Family DSP
WRITE BYTE TO
R/W (LOW)
DATA [7:0]
CS (HIGH)
DS (HIGH)
C S (L O W )
Diagram
D S (LO W )
A[1:0]==00b.
A[1:0]==01b.
A[1:0]==10b.
A[1:0]==11b.
Figure 26
illustrates
45