DA28F640J5-150 Intel, DA28F640J5-150 Datasheet - Page 40

• Manufacturer Part Number: DA28F640J5-150
• Description: Flash Mem Parallel 5V 64M-Bit 8M x 8/4M x 16 150ns 56-Pin SSOP
• Manufacturer: Intel

Specifications of DA28F640J5-150

• Package: 56SSOP
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 5 V
• Sector Size: 128KByte x 64
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: 0 to 70 °C
• Interface Type: Parallel

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
5.0 DESIGN CONSIDERATIONS
5.1
The device will often be used in large memory
arrays. Intel provides five control inputs (CE
CE
memory connections. This control provides for:
To use these control inputs efficiently, an address
decoder should enable the device (see Table 2,
Chip Enable Truth Table ) while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while de-
selected memory devices are in standby mode.
RP#
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2
STS is an open drain output that should be
connected to V
hardware
program, and lock-bit configuration completion. In
default mode, it transitions low after block erase,
program, or lock-bit configuration commands and
returns to High Z when the WSM has finished
executing the internal algorithm. For alternate
configurations of the STS pin, see the Configuration
command.
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the
device is in block erase suspend (with programming
inactive) or in reset/power-down mode.
40
2
, OE#, and RP#) to accommodate multiple
a. Lowest possible memory power dissipation.
b. Complete
should
contention will not occur.
Three-Line Output Control
STS and Block Erase, Program,
and Lock-Bit Configuration
Polling
method
CCQ
be
by a pull-up resistor to provide a
assurance
connected
of
detecting
that
to
block
the
data
0
system
erase,
, CE
bus
1
,
5.3
Flash memory power switching characteristics
require
designers are interested in three supply current
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE
current magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Since Intel
StrataFlash memory devices draw their power from
three V
pin), it is recommended that systems without
separate power and ground planes attach a 0.1 µF
ceramic capacitor between each of the device’s
three V
These high-frequency, low-inductance capacitors
should be placed as close as possible to package
leads on each StrataFlash device. Each device
should have a 0.1 µF ceramic capacitor connected
between its V
low inductance capacitors should be placed as
close as possible to package leads. Additionally, for
every eight devices, a 4.7 µF electrolytic capacitor
should be placed between V
array’s power supply connection. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductance.
5.4
Block erase, program, and lock-bit configuration are
not guaranteed if V
specified operating ranges, or RP#
RP# transitions to V
or lock-bit configuration, STS (in default mode) will
remain low for a maximum time of t
until the reset operation is complete. Then, the
operation will abort and the device will enter
reset/power-down mode. The aborted operation
may
programming, or partially altered after an erase or
lock-bit configuration. Therefore, block erase and
lock-bit configuration commands must be repeated
after normal operation is restored. Device power-off
or RP# = V
CC
ADVANCE INFORMATION
leave
CC
Power Supply Decoupling
V
careful
pins (these devices do not include a V
IL
CC
pins (this includes V
clears the status register.
0
CC
, V
, CE
data
and GND. These high-frequency,
PEN
device
PEN
IL
1
, CE
, RP# Transitions
during block erase, program,
partially
or V
2
, and OE#. Transient
CC
decoupling.
CC
falls outside of the
CCQ
and GND at the
corrupted
) and ground.
V
PLPH
IH
or V
+ t
System
HH
PHRH
after
. If
PP