DA28F640J5-150 Intel, DA28F640J5-150 Datasheet
DA28F640J5-150
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DA28F640J5-150 Summary of contents
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... Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash memory devices take advantage of 400 million units of manufacturing experience since 1988 result, Intel StrataFlash components are ideal for code or data applications where high density and low cost are required. Examples include networking, telecommunications, audio recording, and digital imaging. ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 1.0 PRODUCT OVERVIEW ...................................5 2.0 PRINCIPLES OF OPERATION .....................11 2.1 Data Protection ..........................................12 3.0 BUS OPERATION .........................................12 3.1 Read ..........................................................13 3.2 Output Disable ...........................................13 3.3 Standby......................................................13 3.4 Reset/Power-Down ....................................13 3.5 Read Query................................................14 3.6 Read Identifier Codes.................................14 3.7 Write ..........................................................14 4.0 COMMAND DEFINITIONS ............................14 4.1 Read Array Command................................18 4 ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT FIGURES Figure 1. Intel StrataFlash™ Memory Block Diagram..............................................6 Figure 2. µBGA* Package (64-Mbit and 32-Mbit)9 Figure 3. TSOP Lead Configuration (32-Mbit) ..10 Figure 4. SSOP Lead Configuration (64-Mbit and 32-Mbit) .....................................11 Figure 5. Memory Map .....................................12 Figure 6. Device Identifier Code Memory Map .14 Figure 7 ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 1.0 PRODUCT OVERVIEW The Intel StrataFlash™ memory family contains high-density memories organized as 8 Mbytes or 4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed 16-bit words. The 64-Mbit device is organized as sixty-four 128-Kbyte (131,072 bytes) erase blocks while the 32-Mbits device contains thirty-two 128- Kbyte erase blocks ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT are valid. Likewise, the device has a wake time (t ) from RP#-high until writes to the CUI are PHWL recognized. With RP# at GND, the WSM is reset and the status register is cleared. The Intel StrataFlash memory devices available in several package types. The 64-Mbit is ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 1. Lead Descriptions Symbol Type A INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the device mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A A –A INPUT ADDRESS INPUTS: Inputs for addresses during read and program operations ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 1. Lead Descriptions (Continued) Symbol Type BYTE# INPUT BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on DQ high and low byte. BYTE# high places the device in x16 mode, and turns off the A input buffer ...
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... Intel StrataFlash Memory: 7. 9.79 mm NOTES (Ball I7) and GND (Ball I2) have been removed. Future generations of Intel StrataFlash memory may make use of CC these missing ball locations. 2. The tolerances above indicate projected production accuracy. This product is in the design phase. The package body width and length are subject to change dependent on final die size. Actual die size could shift these values by ± ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 28F016SV 28F160S5 28F032SA 28F320J5 28F016SA 3/5# 3/ PEN RP# RP# RP# RP GND GND GND GND Highlights pinout changes. NOTE: V (Pin 37) and GND (Pin 48) are not internally connected. For future device revisions recommended that these pins be CC connected to their respected power supplies (i ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT NOTE: V (Pin 42) and GND (Pin 15) are not internally connected. For future device revisions recommended that these pins be CC connected to their respected power supplies (i.e., Pin Figure 4. SSOP Lead Configuration (64 Mbit and 32 Mbit) 2.0 PRINCIPLES OF OPERATION ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT enables successful block erasure, PENH PEN programming, and lock-bit configuration. functions associated with altering contents—block erase, program, configuration—are accessed via the CUI and verified through the status register. Commands are written using standard micro- processor write timings ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 2. Chip Enable Truth Table DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled NOTE: 1. See Application Note AP-647 Intel StrataFlash™ Memory Design Guide for typical CE configurations. 2. For single-chip applications CE and CE can strapped to GND. ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 3.5 Read Query The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system interface information, geometry information, and Intel-specific extended query information. 3.6 Read Identifier Codes The read identifier codes operation outputs the ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 3. Bus Operations Mode Notes RP# CE 0,1,2 (10) Read Array 1,2 Enabled Output V or Enabled IH Disable V HH Standby V or Disabled Reset/Power Down Mode Read V or Enabled IH Identifier V HH Codes Read Query V or Enabled Read Status ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 4. Intel StrataFlash™ Memory Command Set Definitions Command Scaleable Bus or Basic Cycles Command Req'd. Set (15) Read Array SCS/BCS 1 Read Identifier SCS/BCS 2 Codes Read Query SCS 2 Read Status SCS/BCS 2 Register Clear Status SCS/BCS 1 Register ...
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... Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 15. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set. ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.1 Read Array Command Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 5. Summary of Query Structure Output as a Function of Device and Mode Device Query start Query data with type/ location maximum device mode in maximum bus width addressing device “x” = ASCII equivalent bus width addresses x16 device/ ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.2 QUERY STRUCTURE OVERVIEW The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized below. See AP- 646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI. ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.3 BLOCK STATUS REGISTER The Block Status Register indicates whether a given block is locked and can be accessed for program/erase operations. On SCS devices that do not implement block locking, BSR.0 will indicate functional block status on partially functional devices. The Block Status Register is accessed from word address 02h within each block ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.4 CFI QUERY IDENTIFICATION STRING The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which vendor-specified command set(s) is(are) supported. Table 9. CFI Identification ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.5 SYSTEM INTERFACE INFORMATION The following device information can optimize system interface software. Table 10. System Interface Information Offset Length (bytes) 1Bh 01h V Logic Supply Minimum CC Program/Erase voltage bits 7–4 bits 3–0 1Ch 01h V Logic Supply Maximum ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.6 DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table 11. Device Geometry Definition Offset Length (bytes) 27h 01h Device Size = 2 28h 02h Flash Device Interface description value 0000h 0002h 2Ah ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.7 PRIMARY-VENDOR SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information. Table 12. Primary Vendor-Specific Extended Query (1) Offset Length (bytes) (P)h 03h Primary extended Query table unique ASCII string “ ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 12. Primary Vendor-Specific Extended Query (Continued) Offset (1) Length (bytes) (P +C)h 01h V Optimum Program/Erase voltage (highest CC performance) bits 7–4 bits 3–0 (P +D)h 01h V [Programming] Optimum Program/Erase voltage PP bits 7–4 bits 3–0 Note: This value is 0000h ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.4 Read Status Register Command The status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT V . Specification t defines the block erase OH WHRH suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the automatically outputs status register data when read (see Figure 8). The CPU can detect the completion of the program event by analyzing the STS pin or status register bit SR ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT A successful set block lock-bit operation requires that the master lock-bit be zero or, if the master lock-bit is set, that RP attempted with HH the master lock-bit set and RP SR.1 and IH SR.4 will be set to “1” and the operation will fail. Set block lock-bit operations while V < ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 15. Configuration Coding Definitions Reserved bits 7– – Reserved DQ 1 – STS Pin Configuration Codes 00 = default, level mode RY/BY# (device ready) indication 01 = pulse on Erase complete 10 = pulse on Program complete 11 = pulse on Erase or Program Complete Configuration Codes 01b, 10b, and 11b are all pulse ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 16. Status Register Definitions WSMS ESS ECLBS bit 7 bit 6 bit 5 High Z When Status Register Bits Busy? No SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy Yes SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed Yes SR ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 17. eXtended Status Register Definitions WBS bit 7 High Z Status Register Bits When Busy? No XSR.7 = WRITE BUFFER STATUS 1 = Write buffer available 0 = Write buffer not available Yes XSR.6–XSR.0 = RESERVED FOR FUTURE ENHANCEMENTS ADVANCE INFORMATION Reserved bits 6– ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Set Time-Out Issue Write Command No E8H, Block Address Read Extended Status Register 0 Write XSR.7 = Buffer Time-Out? 1 Write Word or Byte Count, Block Address Write Buffer Data, Start Address Yes Check Abort Buffer Write Yes ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write 40H, Address Write Data and Address Read Status Register 0 SR Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error 0 1 SR.1 = ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Device Supports Queuing Yes Set Time-Out Issue Block Queue Erase Command 28H, Block Address No Read Extended Status Register Is Queue Erase Block 0=No Available? Time-Out? XSR.7= 1=Yes Another Block Erase? Yes Yes Issue Erase Command 28H ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Program Read or Program? Read Array Program No Data Loop Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data Figure 10. Block Erase Suspend/Resume Flowchart ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error Device Protect Error ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 5.0 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. Intel provides five control inputs ( OE#, and RP#) to accommodate multiple 2 memory connections. This control provides for: a. Lowest possible memory power dissipation. ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT The CUI latches commands issued by system software and is not altered PEN CE transitions, or WSM actions. Its state is read 2 array mode upon power-up, after exit from reset/power-down mode, or after V CC below must be kept at or above V LKO ...
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... NOTICE: This datasheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design *WARNING: Stressing the device beyond the “Absolute (1) Maximum Ratings” ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.4 DC Characteristics Sym Parameter Notes I Input and V Load 1 LI PEN Current I Output Leakage 1 LO Current I V Standby Current 1,3,5 CCS Power-Down CCD CC Current I V Read Current 1,5,6 CCR Program or Set 1,6,7 CCW CC Lock-Bit Current ...
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... NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications specified with the device de-selected. If the device is read or written while in erase suspend mode, the device’s ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 2.4 2.0 Input 0.8 0.45 AC test inputs are driven for a Logic "1" and V OH TTL (2 and V (0 Output timing ends at V TTL IL TTL Figure 13. Transient Input/Output Reference Waveform for V (Standard Testing Configuration) 2.7 Input 1 ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.5 AC Characteristics— Read-Only Operations Versions (All units in ns unless otherwise noted) # Sym Parameter R1 t Read/Write Cycle Time AVAV R2 t Address to Output Delay AVQV Output Delay X ELQV R4 t OE# to Output Delay GLQV R5 t RP# High to Output Delay ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT NOTES: CE low is defined as the first edge that disables the device (see Table 2, Chip Enable Truth Table ). 1 2 Figure 16. AC Waveform for Read Operations ADVANCE INFORMATION that enables the device. CE high is defined at the first edge of CE ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.6 AC Characteristics— Write Operations Versions # Sym RP# High Recovery to WE# (CE ) PHWL PHEL Low (WE#) Low to WE# (CE ELWL WLEL Write Pulse Width Data Setup to WE# (CE ) DVWH DVEH Address Setup to WE# (CE ) AVWH AVEH (WE#) Hold from WE# (CE ) WHEH ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT NOTES: CE low is defined as the first edge that disables the device (see Table 2, Chip Enable Truth Table ). 1 2 STS is shown in its default mode (RY/BY#). 1. V power-up and standby Write block erase, write buffer, or program setup. ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT V IH STS ( RP# ( NOTES: STS is shown in its default mode (RY/BY#). Figure 18. AC Waveform for Reset Operation # Sym. Parameter P1 t RP# Pulse Low Time PLPH (If RP# is tied this specification is not applicable RP# High to Reset during Block Erase, Program, or ...
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... INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.7 Block Erase, Program, and Lock-Bit Configuration Performance # Sym Parameter W16 t Write Buffer Byte Program Time WHQV1 t EHQV1 W16 t Write Buffer Word Program Time WHQV2 t EHQV2 W16 t Byte Program Time (Using WHQV3 t Word/Byte Program Command) ...
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... Mbit) 320 = x8/x16 (32 Mbit) Order Code by Density 32 Mbit DA28F320J5-120 G28F320J5-120 E28F320J5-120 52 0 Voltage ( 5V/5V Product Family J = Intel StrataFlash 2 bits-per-cell Valid Operational 64 Mbit 2.7 V – 3 DA28F640J5-150 Yes G28F640J5-150 Yes Yes ADVANCE INFORMATION Access Speed (ns) (120, 150 PEN TM memory, Conditions ± 10% ...
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... AP-647 Intel StrataFlash™ Memory Design Guide NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ...