DA28F640J5-150 Intel, DA28F640J5-150 Datasheet - Page 4

• Manufacturer Part Number: DA28F640J5-150
• Description: Flash Mem Parallel 5V 64M-Bit 8M x 8/4M x 16 150ns 56-Pin SSOP
• Manufacturer: Intel

Specifications of DA28F640J5-150

• Package: 56SSOP
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 5 V
• Sector Size: 128KByte x 64
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: 0 to 70 °C
• Interface Type: Parallel

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
FIGURES
4
Figure 1. Intel StrataFlash™ Memory Block
Figure 2. µBGA* Package (64-Mbit and 32-Mbit)9
Figure 3. TSOP Lead Configuration (32-Mbit) ..10
Figure 4. SSOP Lead Configuration (64-Mbit
Figure 5. Memory Map .....................................12
Figure 6. Device Identifier Code Memory Map .14
Figure 7. Write to Buffer Flowchart...................34
Figure 8. Byte/Word Program Flowchart ..........35
Figure 9. Block Erase Flowchart ......................36
Figure 10. Block Erase Suspend/Resume
Figure 11. Set Block Lock-Bit Flowchart...........38
Figure 12. Clear Block Lock-Bit Flowchart........39
Figure 13. Transient Input/Output Reference
Figure 14. Transient Input/Output Reference
Figure 15. Transient Equivalent Testing Load
Figure 16. AC Waveform for Read Operations .47
Figure 17. AC Waveform for Write Operations .49
Figure 18. AC Waveform for Reset Operation ..50
Revision
09/01/97
09/17/97
12/01/97
Date of
1/31/98
Diagram..............................................6
and 32-Mbit) .....................................11
Flowchart..........................................37
Waveform for V
(Standard Testing Configuration)......45
Waveform for V
Circuit ...............................................45
Version
-001
-002
-003
-004
CCQ
CCQ
= 5.0 V ± 10%
= 2.7 V 3.6V .....45
Original Version
Modifications made to cover sheet
V
I
Order Codes specification change added
The BGA* chip-scale package in Figure 2 was changed to a 52-ball
package and appropriate documentation added. The 64-Mb BGA
package dimensions were changed in Figure 2. Changed Figure 4 to
read SSOP instead of TSOP.
CCS
CC
/GND Pins Converted to No Connects specification change added
, I
CCD
REVISION HISTORY
, I
CCW
, and I
CCE
TABLES
specification change added
Table 1. Lead Descriptions.................................7
Table 2. Chip Enable Truth Table.....................13
Table 3. Bus Operations...................................15
Table 4. Intel StrataFlash™ Memory Command
Table 5. Summary of Query Structure Output as
Table 6. Example of Query Structure Output of
Table 7. Query Structure ..................................20
Table 8. Block Status Register .........................21
Table 9. CFI Identification ................................22
Table 10. System Interface Information ............23
Table 11. Device Geometry Definition ..............24
Table 12. Primary Vendor-Specific Extended
Table 13. Identifier Codes ................................26
Table 14. Write Protection Alternatives ............30
Table 15. Configuration Coding Definitions.......31
Table 16. Status Register Definitions ...............32
Table 17. eXtended Status Register Definitions33
Description
ADVANCE INFORMATION
Set Definitions ...................................16
a Function of Device and Mode .........19
a x16- and x8-Capable Device...........19
Query.................................................25