GS842Z36AGB-150 GSI TECHNOLOGY, GS842Z36AGB-150 Datasheet

GS842Z36AGB-150

Manufacturer Part Number

GS842Z36AGB-150

Description

58M6829

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS842Z36AGB-150.pdf (29 pages)

Specifications of GS842Z36AGB-150

Memory Size

4Mbit

Memory Configuration

128K X 36

Clock Frequency

150MHz

Access Time

10ns

Supply Voltage Range

2.3V To 2.7V, 3V To 3.6V

Memory Case Style

BGA

No. Of Pins

119

Rohs Compliant

Yes

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119-Bump BGA

Commercial Temp

Industrial Temp

Features

• 256K x 18 and 128K x 36 configurations

• User configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Fully pin compatible with both pipelined and flow through

• Pin-compatible with 2M, 8M, and 16M devices

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 119-bump BGA package

• RoHS-compliant package available

Functional Description

The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.04b 1/2009

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization

NtRAM™, NoBL™ and ZBT™ SRAMs

Through

Pipeline

3-1-1-1

2-1-1-1

4Mb Pipelined and Flow Through

Flow

Synchronous NBT SRAMs

tCycle

Parameter Synopsis

335 mA

210 mA

1/29

5.5 ns

3.2 ns

9.1 ns

–180

8 ns

310 mA

190 mA

6.0 ns

3.5 ns

8.5 ns

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS842Z18/36AT may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS842Z18/36AT is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump BGA package.

10 ns

–166

280 mA

165 mA

6.6 ns

3.8 ns

10 ns

12 ns

–150

GS842Z18/36AB-180/166/150/100

190 mA

135 mA

4.5 ns

10 ns

12 ns

15 ns

–100

2.5 V and 3.3 V V

180 MHz–100 MHz

3.3 V V

DDQ

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