74HC107D NXP Semiconductors, 74HC107D Datasheet - Page 5

• Manufacturer Part Number: 74HC107D
• Description: Flip Flops DUAL J-K W/NEG-EDGE TRIG
• Manufacturer: NXP Semiconductors

Specifications of 74HC107D

• Number Of Circuits: 2
• Logic Family: HC
• Logic Type: J-K Negative Edge Triggered Flip Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 16 ns at 5 V
• High Level Output Current: - 5.2 mA
• Supply Voltage (max): 6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-108
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 2 V
• Lead Free Status / Rohs Status: Details
• Other names: 74HC107D,652

Philips Semiconductors
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: standard
I
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
December 1990
CC
SYMBOL PARAMETER
t
t
t
t
t
t
t
t
t
f
PHL
PHL
PHL
THL
W
W
rem
su
h
max
Dual JK flip-flop with reset; negative-edge trigger
category: flip-flops
/ t
/ t
/ t
/ t
TLH
PLH
PLH
PLH
propagation delay
propagation delay
propagation delay
output transition time
clock pulse width
reset pulse width
removal time
set-up time
hold time
maximum clock pulse
r
= t
nCP to nQ
nCP to nQ
nR to nQ, nQ
HIGH or LOW
LOW
nR to nCP
nJ, nK to nCP
nJ, nK to nCP
frequency
f
= 6 ns; C
L
= 50 pF
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
80
16
14
80
16
14
60
12
10
100
20
17
3
3
3
6.0
30
35
min.
52
19
15
52
19
15
52
19
15
19
7
6
22
8
6
22
8
6
19
7
6
22
8
6
23
70
85
typ. max. min. max. min. max.
6
2
2
25
160
32
27
160
32
27
155
31
26
75
15
13
T
amb
5
74HC
100
20
17
100
20
17
75
15
13
125
25
21
3
3
3
4.8
24
28
40 to 85
( C)
200
40
34
200
40
34
195
39
33
95
19
16
120
24
20
120
24
20
4.0
20
24
90
18
15
150
30
26
3
3
3
40 to 125
240
48
41
240
48
41
235
47
40
110
22
19
.
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
UNIT
74HC/HCT107
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
V
TEST CONDITIONS
(V)
Product specification
CC
WAVEFORMS
Fig.6
Fig.6
Fig.7
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
Fig.6
Fig.6