GAL26CV12B-20LP Lattice, GAL26CV12B-20LP Datasheet - Page 2

• Manufacturer Part Number: GAL26CV12B-20LP
• Description: SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD
• Manufacturer: Lattice

Specifications of GAL26CV12B-20LP

• Logic Family: GAL
• Number Of Macrocells: 12
• Maximum Operating Frequency: 62.5 MHz
• Number Of Programmable I/os: 12
• Delay Time: 20 ns
• Operating Supply Voltage: 5 V
• Supply Current: 130 mA
• Maximum Operating Temperature: + 75 C
• Minimum Operating Temperature: 0 C
• Package / Case: PDIP-28
• Mounting Style: Through Hole
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / Rohs Status: No

• HIGH PERFORMANCE E
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
• E
• TWELVE OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL26CV12, at 7.5 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
performance 28-pin PLD available on the market. E
offers high speed (<100ms) erase times, providing the ability to
reprogram or reconfigure the device quickly and efficiently.
Expanding upon the industry standard 22V10 architecture, the
GAL26CV12 eliminates the learning curve typically associated with
using a new device architecture. The generic architecture provides
maximum design flexibility by allowing the Output Logic Macrocell
(OLMC) to be configured by the user. The GAL26CV12 OLMC is
fully compatible with the OLMC in standard bipolar and CMOS
22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data
retention in excess of 20 years are specified.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
26cv12_03
Features
Description
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
— 90 mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Uses Standard 22V10 Macrocells
— Maximum Flexibility for Complex Logic Designs
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
2
) floating gate technology to provide the highest
®
Advanced CMOS Technology
2
CMOS
®
TECHNOLOGY
2
technology
1
Functional Block Diagram
Pin Configuration
VCC
I
I
I
I
I
I
11
5
7
9
I/CLK
12
GAL26CV12
4
I
I
I
I
I
I
I
I
I
I
I
I
Top View
14
PLCC
2
High Performance E
16
28
18
26
25
23
21
19
GAL26CV12
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
Generic Array Logic™
PRESET
10
12
12
10
8
8
8
8
8
8
8
8
RESET
I/CLK
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
Vcc
I
I
I
I
I
I
I
I
I
I
I
I
1
7
14
26CV12
2
GAL
DIP
CMOS PLD
June 2000
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
INPUT
28
21
15
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q