WGCE5039 Intel, WGCE5039 Datasheet - Page 9

• Manufacturer Part Number: WGCE5039
• Manufacturer: Intel

Specifications of WGCE5039

• Lead Free Status / Rohs Status: Compliant

2.0
The register map is arranged as 16 byte-wide read/write registers grouped by functional block. The registers may
be written to and read-back from either sequentially (for lowest overhead) or specifically (for maximum flexibility).
A significant number of bits are used for test and evaluation purposes only and are fixed at logic ‘0’ or ‘1’. The
correct programming for these test bits is shown in the table below. It is essential that these values are programmed
for correct operation. When the contents of the registers are read back the value of some bits may have changed
from their programmed value. This is due to the internal automatic control which can update registers. Any changes
can be ignored.
Read only bits are marked with an asterisk (*). Any data written to these bits will be ignored.
Registers are set to default settings on applying power. These conditions are shown below and in the applicable
tables.
X* denotes a read only test bit
Register
Register Map and Programming
C
D
A
B
E
F
0
1
2
3
4
5
6
7
8
9
PLL
PLL
PLL
PLL
RF Front End
Base Band
Base Band
Base Band
Local Oscillator
Local Oscillator
Local Oscillator
Local Oscillator
Local Oscillator
Local Oscillator
Local Oscillator
General
Block
BLF*
FLF*
PLF
BF7
PD
Table 2 - Register Map
X*
X*
X*
X*
X*
2
0
0
1
1
1
7
Intel Corporation
BG3
CLR
CE5039
BF6
2
LF
2
X*
X*
X*
0
1
1
0
0
1
1
14
6
9
BG2
BF5
2
C1
SF
P0
2
X*
0
1
1
1
1
1
0
1
13
5
BR4
BG1
BF4
2
C0
2
0
0
0
0
1
1
1
1
1
0
12
Function
4
BR3
BG0
BF3
2
R3
2
X*
0
1
0
0
0
1
0
0
0
11
3
BR2
BF2
2
R2
2
X*
0
1
0
0
0
0
0
0
0
0
10
2
LEN
BR1
BF1
R1
X*
2
2
0
0
0
1
0
0
0
0
0
9
1
Data Sheet
BR0
BF0
R0
X*
2
2
0
0
0
0
0
1
0
0
0
0
8
0