WGCE5039 Intel, WGCE5039 Datasheet - Page 8

• Manufacturer Part Number: WGCE5039
• Manufacturer: Intel

Specifications of WGCE5039

• Lead Free Status / Rohs Status: Compliant

The output of the phase detector feeds a charge pump which combined with an external loop filter integrates the
current pulses to control the varactor voltage. The charge pump current is automatically varied by the VCO control
logic to compensate for VCO gain variations that are dependent on selected sub band. The varactor control voltage
is externally coupled to the oscillator section through the input pin Vvar.
1.4
All programming for the CE5039 is controlled by an I
formats.
Data and Clock are fed in on the SDA and SCL lines respectively as defined by I
either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into
write mode if it is logic ‘0’, and read mode if it is logic ‘1’. The I
format.
The CE5039 contains 16 control registers. These registers are read/write registers. These registers are addressed
as sub-addresses on the I
access sequential write and read as shown below.
Random Access Single Write
Random Access Sequential Write
Stop
Random Access Single Read
Random Access Sequential Read
W
A
N
A SLEEP pin is provided. This powers down all sections of the chip including the crystal oscillator and I
The RF bypass function will be operational in this mode providing it has been previously enabled through the I
interface.
I
Stop
Stop
Stop
Stop
2
Write bit
Acknowledge Bit
Not Acknowledge
C Interface
Start
Start
Start
Start
Device
Address
Device
Address
Device
Address
Device
Address
2
W A
W A
W A
W A
C bus. Registers can be addressed as random access single write/read or random
Register
Address
Register
Register
Register
Address
Address
Address
N
N
N
N
A
A
A
A
Start
Start
Register
Register
Intel Corporation
Data
Data
N
N
CE5039
Address
Address
Device
Device
2
8
C data bus and is compatible with 3V3 standard mode
A
A
Stop
Register
R
R
2
C address is fixed at C0 (Write)/C1(Read) in hex
Data
N+1
A
A
Register
Register
Data
Data
...
N
N
Register
N+M
Data
N
A
2
C bus format. The device can
Stop
...
A
Register
Data
N+M
Stop
N
Data Sheet
2
Stop
C interface.
2
C