TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 21

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

BDC1J1(V1)
Symbol
BA(7-0)
BACLK
BAPAR
BASPE
J3, K4, K3,
J1, K2, L4,
Lead No. I/O/P
Proprietary TranSwitch Corporation Information for use Solely by its Customers
K1, L3
M1
M2
E2
L1
I/O(T) TTL3V/
I/O(T) TTL3V/
O(T) CMOS3V
O(T) CMOS3V
I
CMOS3V
CMOS3V
TTL3V B Drop Bus C1J1V1 Indications: An active high timing signal that
Type
8mA
8mA
8mA
8mA
carries STM-1/STS-3 frame and SPE information. This signal works
in conjunction with the BDSPE signal. The C1 pulse identifies the
location of the first C1 byte in the STM-1 and STS-3 signals, when
BDSPE signal is low. The J1 pulse identifies the starting location of
the J1 byte in the STM-1 VC-4 signal when BDSPE is high. Three J1
pulses identify the starting location for each of the three STS-1 sig-
nals in the STS-3 signal. A single V1 pulse identifies the location for
the V1/V2 bytes in the TUG-3 within the VC-4. Three V1 pulses
identify the location of the V1/V2 bytes within each of the three
STS-1s. The V1 pulses may be absent. In which case the mapper
will detect the starting location of the multiframe within the H4 byte.
B Add Bus Clock: When the add bus timing mode is selected (lead
ABUST is low), this input must be provided for add bus timing. This
clock operates at 19.44 MHz for STM-1/STS-3 operation. The add
bus SPE indication (BASPE), and the C1J1V1 indication
(BAC1J1V1) are clocked in on falling edges of this clock. Add bus
byte-wide data (BA7-BA0), add indicator (BADD), and the parity bit
(BAPAR) are clocked out on rising edges of the clock during the time
slots that correspond to the selected TU/VT. When drop bus timing
is selected (lead ABUST is high), and lead ABTE is low, this clock,
which is derived from the like-named drop bus is an output. When
lead ABTE is high in the drop bus timing mode, this lead is disabled
and forced to the high impedance state.
B Add Bus Parity Bit: An odd or even parity output signal that is
calculated over the byte-wide add data. When drop bus timing is
selected (lead ABUST is high), and lead ABTE is low, parity may be
also calculated for the C1J1V1 and SPE signals. This lead is only
active when there is data being added to the add bus.
B Add Bus Data Byte: Byte-wide data that corresponds to the
selected TU/VT. The first bit transmitted (added) corresponds to bit 7
which is lead J3.
B Add Bus SPE Indicator: When the add bus timing mode is
selected, this signal must be provided for add bus timing. This signal
must be high during each byte of the STM-1/STS-3 payload, and low
during Transport Overhead byte times. When drop bus timing is
selected (lead ABUST is high), and lead ABTE is low, this signal,
which is derived from the like-named drop bus is an output. When
lead ABTE is high in the drop bus timing mode, this lead is disabled
and forced to the high impedance state.
DATA SHEET
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Name/Function
TXC-04222-MB, Ed. 6
TXC-04222
TEMx28
June 2003