TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet
TXC-04222-AIOG
Specifications of TXC-04222-AIOG
Related parts for TXC-04222-AIOG
TXC-04222-AIOG Summary of contents
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... B - side drop bus B - side add bus U.S. and/or foreign patents issued or pending Copyright 2003 TranSwitch Corporation PHAST, TEMx28, TranSwitch and TXC are registered trademarks of TranSwitch Corporation TranSwitch Corporation Tel: 203-929-8810 28 Channel Dual Bus High Density Mapper DESCRIPTION The TEMx28 multiplexer, terminal multiplexer, and dual and single unidirectional ring applications ...
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... They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET TABLE OF CONTENTS ...
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... Asynchronous Mapping ....................................................................................... 14 4 VC-11 to VC-12 Cross Mapping ............................................................................................ 15 5 Application Using the TEMx28 TXC-04222 ........................................................................... 16 6 TEMx28 TXC-04222 376-Lead Plastic Ball Grid Array Package Lead Diagram ................... 17 7 Channels DS1/E1 Transmit Rail Interface Timing ....................................................... 32 8 Channels DS1/E1 Transmit NRZ Interface Timing ...................................................... 33 9 Channels Transmit VT/TU Interface Timing -Gapped Pointer Bytes ........................... 34 10 Channels Transmit VT/TU Interface Timing-Gapped Pointer & ...
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... A software polling register and summary alarm bit status are also provided. One second measurements are performed for alarms and counters. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET ...
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... Independent VT1.5/TU-11 or VT2/TU12 Selection per Channel for both Drop and Add Buses • Cross Mapping: DS1 mapped into VT1.5/TU-12 • SONET/SDH Operating Formats • STS-3 STS-1 (19.44 Mbyte/s) • STM-1 VC-4/TUG-3/TUG-2 (19.44 Mbyte/s) • STM-1 AU-3s (19.44 Mbyte/s) DATA SHEET - 5 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... RFI Detector • BIP-2 Bit/Block Error Counter Option • Signal Label Mismatch, Unequipped, and VC AIS detection • Detection/Recovery: 5 events • N2 Byte • Tandem Connection Option • Trail Trace Message Comparison against Microprocessor Written Message TXC-04222-MB, Ed. 6 June 2003 DATA SHEET - 6 of 246 - ...
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... TC AIS Generation •TC Unequipped Generation • Overhead Single Byte Insertion • All Bytes • Test purpose • Unequipped Generation (per Channel) • Supervisory Unequipped Generation Option • Transmit AIS Generation DATA SHEET - 7 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... High Z all Leads (except Boundary Scan Output) • PRBS Generator and Analyzer 15 • defined in O.151 and T1M1.3/92-006R3 or QRSS (2 • Drop or Add Direction Placement • Single Bit Error Generation for Transmit REI and BIP-2 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET 20 -1) as defined in ANSI T1.403-1195 246 - ...
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... Bus A Pointer Generation Insert B Transmit OH Bytes Add Add Construct Bus Bus TU Signals Interface Bus B Pointer Generation Figure 1. TEMx28 TXC-04222 Block Diagram DATA SHEET Drop TC Byte Destuff Desynchronizer Processing n TU/VTs Drop TC Byte Destuff Desynchronizer Processing n TU/VTs VT/TU Payload TC States for VT/TU Payload ...
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... V1 pulse. For STS-3 operation, three V1 pulses must be present every four frames. Each of the three V1 pulses must be present three clock cycles after the corresponding J1 pulse, when the SPE signal is high. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET ...
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... Bits 1 and 2 in the K4 byte carry an extended signal label and information pertaining to the payload position within the Virtual Concatenation channel. The Virtual Concatenation channel will be assigned to n VT/TUs based on the data bandwidth required for the application. DATA SHEET - 11 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... TEMx28 device. The device driver insulates the application from the internal details of the device register usage and provides a higher level of abstraction. Particularly powerful are the default configurations provided within the driver that allow one single command to bring the device to operational mode. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET - 12 of 246 - ...
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... Normal = 0110, 1110, 0010, 0100 or 0111 New = 1001, 0001, 1101, 1011 or 1000 Positive Justification = Invert five I-bits Negative Justification = Invert five D-bits Pointer Range = 0 - 103 decimal - 13 of 246 - TEMx28 TXC-04222 TU-11/VT1.5 26 bytes 26 bytes V3 (Action) 26 bytes V4 (Reserved) 26 bytes 108 Bytes Size TXC-04222-MB, Ed. 6 June 2003 ...
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... REI = Remote Error Indication (formerly FEBE, Far End Block Error Indication) RFI = Remote Failure Indication Signal Label RDI = Remote Defect Indication (formerly FERF, Far End Receive Failure Indication) Figure 3. 2048 kbit/s Asynchronous Mapping TXC-04222-MB, Ed. 6 June 2003 DATA SHEET VC- bytes (2048 kbit/s Data ...
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... Data) K4(Z7) 34 bytes (2048 kbit/s Data) 500 s When mapping a VC- VC-12, the VC-11 is adapted by adding fixed stuff with even parity 246 - TEMx28 TXC-04222 TU-12/VT2 V1 (Pointer Byte) 35 bytes V2 (Pointer Byte) 35 bytes V3 (Action) 35 bytes V4 (Reserved) 35 bytes 144 Bytes TXC-04222-MB, Ed. 6 June 2003 ...
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... T1Fx8 (TXC-03108) - E1Fx8 (TXC-03109) - QE1F-Plus (TXC-03114) - PHAST -3N (TXC-06103) - T3BwP (TXC-06826) TXC-04222-MB, Ed. 6 June 2003 DATA SHEET EAST TERMINAL PHAST -3N (TXC-06103) and and Bus Drivers/Receivers TEMx28 TEMx28 TXC-04222 TXC-04222 channels channels Application Using the TEMx28 TXC-04222 - 16 of 246 - STM-1 or STS-3 A DROP A ADD ...
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... This is the bottom view. The leads are solder balls. See Figure 42 for package information. Some signal Symbols have been abbreviated to fit the space available. The Symbols are shown in full in the Lead Descriptions section. Figure 6. TEMx28 TXC-04222 376-Lead Plastic Ball Grid Array Package Lead Diagram DATA SHEET A10 ...
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... AD(7-0) E1, F2, I TTL3V G3, H4, F1, G2, H3, J4 *See Input, Output and Input/Output Parameters section below for Type definitions. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET I/O VDD1: +1.8 volt supply voltage, 5%. P VDD2: +3.3 volt supply voltage, 5%. This supply voltage should be powered up prior to the 1.8 V (VDD1) supply voltage or at the same time ...
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... Transport Overhead byte times. When drop bus timing is selected (lead ABUST is high), and lead ABTE is low, this signal, which is derived from the like-named drop bus is an output. When lead ABTE is high in the drop bus timing mode, this lead is disabled 246 - TEMx28 TXC-04222 Name/Function TXC-04222-MB, Ed. 6 June 2003 ...
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... C2, D2, C1, F4 BDSPE F3 I TTL3V B Drop Bus SPE Indicator: A signal that is active high for each TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Type * A Add Bus C1J1V1 Indications: An active high timing signal that carries STM-1/STS-3 frame and SPE information. This signal works 8mA in conjunction with the AASPE signal ...
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... ABUST is high), and lead ABTE is low, this signal, which is derived from the like-named drop bus is an output. When lead ABTE is high in the drop bus timing mode, this lead is disabled and forced to the high impedance state 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... P20, M19, L21, J22, G22, G20, E21, E19, D18, B18, C16, A16, A14, B12, D11, C9, B7, A4, C5 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Type Name/Function B Add Bus C1J1V1 Indications: An active high timing signal that carries STM-1/STS-3 frame and SPE information. This signal works 8mA in conjunction with the AASPE signal ...
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... When control bits TnLINT1/0 are set to 01, an external loss of signal (when control bit EXnLOS (bit 1, register X+003H clocked in on this lead. When control bit EXnLOS external coding violations can be clocked in on this lead. Lead W13 is TNI1/TLOS1 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... VTFA2 R4 O CMOS3V 4 mA TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Name/Function must remain an active high for the mapper to function. This lead is pulled high by an internal pull-up to VDD2. It must be left floating or held high. nizer operation and for other internal functions, such as generating a receive AIS signal ...
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... MOTO Action L Intel bus interface H Motorola bus interface Name/Function Address Bus (Motorola/Intel Buses): These address line inputs are used for accessing memory map locations for a read/write cycle. A14 (lead AB6) is the most significant bit 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... BOUNDARY SCAN INTERFACE Symbol Lead No. I/O/P Type TCK AA3 I TTL3V TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Type Data Bus (Motorola/Intel Buses): Bidirectional data lines used for transferring data to or from a memory map location. D7 (lead AA5) is 8mA the most significant bit. Select: An active low enables data transfers between the micropro- cessor and the memory map location during a read/write cycle ...
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... TAP controller to take control of some of the TEMx28 output leads. Name/Function only. These leads have an internal pull down to GND and should be held low. TranSwitch Test Output Leads: For TranSwitch testing purposes only. These leads should be left open (floating 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... Notes: 1. Typical values are based on measurements made with nominal voltages Maximum values are based on measurements made at maximum voltages All 28 channels are configured as E1 and are being added and dropped in Dual Protection Ring Mode. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Symbol Min ...
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... DD2 3.15 < V < 3.45 DD2 V = 3.45 DD2 Test Conditions 3.15 < V < 3.45 DD2 3.15 < V < 3.45 DD2 DD2 V =3.45; Input = 0 volts DD2 Test Conditions 3.15 < V < 3.45 DD2 3.15 < V < 3.45 DD2 3.45; Input = 3.45 volts DD2 TXC-04222-MB, Ed. 6 June 2003 ...
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... RISE t FALL Leakage tristate Output capacitance OUTPUT PARAMETERS FOR CMOS3V 8mA Parameter Min Output capacitance -12 RISE t FALL Leakage tristate TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Typ Max Unit V 0.4 V 8 ±10 nA ±1 A 3.1 pF Typ Max Unit 7 0 -40 mA ± ...
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... DD2 0 to 3.3 V input 3.15 -4.0 DD2 3.15 4.0 DD2 LOAD LOAD Unit Test Conditions V 3.15 < V < 3.45 DD2 V 3.15 < V < 3.45 DD2 0 to 3.3 V input; see Note 3.15 -8.0 DD2 3.15 8.0 DD2 LOAD LOAD TXC-04222-MB, Ed. 6 June 2003 ...
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... TPIn/TNIn data hold time after TCIn E1 Interface Parameter TCIn Clock period TCIn clock low time TCIn clock high time TPIn/TNIn data setup time before TCIn TPIn/TNIn data hold time after TCIn TXC-04222-MB, Ed. 6 June 2003 DATA SHEET t CYC t t PWH PWL ...
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... Typ t 580.0 647.7 CYC t 280 PWL t 280 PWH t 15 SU(1) t 2.0 H( SU(2) t 2.0 H(2) Symbol Min Typ t 435.0 488.28 CYC t 150 PWL t 150 PWH t 15 SU(1) t 2.0 H( SU(2) t 2.0 H( 246 - TEMx28 TXC-04222 Note Max Unit Max Unit TXC-04222-MB, Ed. 6 June 2003 ...
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... TVTCn clock low time TVTCn clock high time TVTCn clock frequency (nominal) TVTDn data setup time before TVTCn TVTDn data hold time after TVTCn VTFA/B2 delay from TVTCn Multiframe Time VTFA/B2 pulse width TXC-04222-MB, Ed. 6 June 2003 DATA SHEET V1 Byte t pw(1) t CYC ...
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... PW(2) Symbol Min t 411.52 CYC t 205.76 PWL t 205.76 PWH 2 SU(2) t 500 PW(1) t 462.96 PW( 246 - TEMx28 TXC-04222 Note Typ Max Unit 9927.92 ns 9670.72 ns 9670.72 ns 1.600 MHz 500 s 875.0 ns Typ Max Unit 7561.68 ns 7355.92 ns 7355.92 ns 2.176 MHz 500 s 772 ns TXC-04222-MB, Ed. 6 June 2003 ...
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... RCOn clock low time RCOn clock high time RPOn/RNOn data delay after RCOn E1 Interface Parameter RCOn clock period RCOn clock low time RCOn clock high time RPOn/RNOn data delay after RCOn TXC-04222-MB, Ed. 6 June 2003 DATA SHEET t CYC t t PWH PWL ...
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... PWL OD Symbol Min t 637 CYC t 320 PWL t 318 PWH t -5.0 OD Symbol Min t 480 CYC t 233 PWL t 247 PWH t -5 246 - TEMx28 TXC-04222 Note Typ Max Unit 658 ns 335 ns 321 ns 5.0 ns Typ Max Unit 498 ns 248 ns 248 ns 5.0 ns TXC-04222-MB, Ed. 6 June 2003 ...
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... VT 2 INTERFACE Parameter RVTCn clock period RVTCn clock low time RVTCn clock high time RVTCn clock frequency (nominal) RVTFn delay after RVTCn RVTDn delay after RVTCn Multiframe Time RVTFn pulse width TXC-04222-MB, Ed. 6 June 2003 DATA SHEET V1 byte t pw(1) t CYC t t PWL ...
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... PWH t 13.1 D(1) t 14.0 D(2) t 500 PW(1) t 422.2 PW( 246 - TEMx28 TXC-04222 Note D(2) Typ Max Unit 9930.1 ns 9668.0 ns 276.6 ns 1.600 MHz 14.5 ns 14.5 ns 500 s 873 ns Typ Max Unit 7425.7 ns 7236.4 ns 189.3 ns 2.176 MHz 14.5 ns 14.5 ns 500 s 770 ns TXC-04222-MB, Ed. 6 June 2003 ...
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... A/BAC1J1V1 delay from A/BACLK A/BASPE delay from A/BCLK A/B(7-0) and A/BAPAR data /parity out valid delay from A/BACLK A/BADD delay from A/BACLK Note: All output times are measured with the 50 pf load capacitance. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET TU/VT J1 Byte Data ...
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... CYC t SU(1) t H(1) t SU(2) t H(2) t SU(3) t H(3) t OD(1) t OD(2) t OD(4) t OD( 246 - TEMx28 TXC-04222 Data STS-1 #3 STS STS STS-1 #1 Min Typ Max Unit 51. 5.0 ns 2.0 ns 5.0 ns 3.0 ns 5.0 ns 3.0 ns 4.0 21.0 ns 4.0 15.0 ns 4.0 18.0 ns 4.0 15.0 ns TXC-04222-MB, Ed. 6 June 2003 ...
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... A/BAC1J1V1 delay from A/BACLK A/BASPE delay from A/BCLK A/B(7-0) and A/BAPAR data /parity out valid delay from A/BACLK A/BADD delay from A/BACLK Note: All output times are measured with the 50 pf load capacitance. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET TU/VT J1 Byte Data ...
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... OD(2) OD(3) TU/VT Selected t OD(4) Symbol t CYC t SU(1) t H(1) t SU(2) t H(2) t SU(3) t H(3) t OD(1) t OD(2) t OD(4) t OD( 246 - TEMx28 TXC-04222 Min Typ Max Unit 51. 5.0 ns 2.0 ns 5.0 ns 3.0 ns 5.0 ns 3.0 ns 4.0 21 4.0 18.0 ns 4.0 15.0 ns TXC-04222-MB, Ed. 6 June 2003 ...
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... A(7-0)/APAR data /parity to tristate delay from ACLK ADD add indicator delayed from ACLK A(7-0)/APAR data /parity out tristate to driven delay from ACLK Note: All output times are measured with the specified load capacitance. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET t H(2) ...
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... OD(3) TU/VT Selected t OD(4) t OD(1) Symbol Load t CYC t SU(1) t H(1) t SU(2) t H(2) t OD(2) 50pF t OD(3) t 50pF OD(1) t 50pF OD( 246 - TEMx28 TXC-04222 Occurs every four frames when enabled V1 Min Typ Max Unit 51. 5.0 ns 5.0 ns 5.0 ns 5 TXC-04222-MB, Ed. 6 June 2003 ...
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... RDY float time after SEL RDY pulse width Data output valid delay after RD Data output valid delay after RDY Data output tristate to driven delay after RD Note: All output times are measured with a maximum 25 pF load capacitance. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Address t D(5) ...
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... Note: All output times are measured with a maximum 25 pF load capacitance. DATA SHEET t H(1) Address t H(2) Data t SU(2) t SU(4) t SU(3) t PW(1) t D(2) t PW(2) Symbol Min t 3.0 SU( H( SU( H( SU( PW( D( PW( SU( 246 - TEMx28 TXC-04222 t F Typ Max Unit 1 TXC-04222-MB, Ed. 6 June 2003 ...
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... D(7-0) data output tristate to drive delay after SEL , (See Note 2) WR/LDS Notes: 1. All output times are measured with a maximum 25 pF load capacitance. 2. Measured with respect to the later of SEL or WR/LDS falling edge. 3. Measured with respect to the earlier of TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Address t D(1) t ...
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... Measured with respect to the earlier of DATA SHEET Address t SU(2) Data t SU(1) t PW(1) t D(4) t D(2) Symbol t SU(1) t H(1) t WR/LDS SU(2) t WR/LDS H(2) t PW(1) t WR/LDS D( (See Note 2) t D(4) SEL or WR/LDS rising edge 246 - TEMx28 TXC-04222 t H( Min Typ Max Unit 1.2 us TXC-04222-MB, Ed. 6 June 2003 ...
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... TMS hold time after TCK TDI setup time before TCK TDI hold time after TCK TDO delay from TCK (see Note) TRS Pulse Width Note: The output time (TDO) is measured with a maximum load capacitance. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Figure 25. Boundary Scan Timing PWH t ...
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... A and B Add buses. The other drop bus monitors the VT/TU. Timing for the TU/ added to the A (or B) Add bus is derived from either the A (or B) Drop bus, or from the A (or B) Add bus. DATA SHEET - 51 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... A and B Drop and Add buses. A Drop Bus Reset operation should be performed after modifying the STS-3 bit. See DRESET bit at address 039H in the Memory Map Description. STS-3 Format or STM-1 AU-3 Format STM-1 VC4 Format STS-3 STS-1/STM-1 VC-4 Format Selection TXC-04222-MB, Ed. 6 June 2003 DATA SHEET TnSEL0 RnSEL ...
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... AU-3/TUG-3 A, STS-1 #1 AU-3/TUG-3 B, STS-1 #2 AU-3/TUG-3 C, STS-1 #3 TU/VT Group Number 1 TU/VT Group Number 2 TU/VT Group Number 3 TU/VT Group Number 4 TU/VT Group Number 5 TU/VT Group Number 6 TU/VT Group Number 7 TU/VT Number 1 TU/VT Number 2 TU/VT Number 3 TU/VT Number 4 (VT1.5/TU-11 format) TXC-04222-MB, Ed. 6 June 2003 ...
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... TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Action Add bus timing selected. Drop bus timing selected. Bus Timing Selection Action on an Alarm Not used. No latched alarm event indication, or interrupt indication. Alarm sets latched alarm on positive transitions of the alarm. ...
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... The Persistent (FM) status bit the alarm is active but did not become active during the previous one-second interval. DATA SHEET POSITIVE TRANSITION INTR1, INTR0=10 Set On Pos. Transition Clear On Read NEGATIVE TRANSITION INTR1, INTR0=01 Set On Neg. Transition Clear On Read POSITIVE/NEGATIVE TRANSITION INTR1, INTR0=11 Set On Transition Clear On Read - 55 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... VT/TU selected (e.g., channel 5 detects a signal label mismatch alarm). A polling bit in the B drop polling regis- ters (094H - 097H) sets to 1 when a channel detects a B drop side alarm for the VT/TU selected (e.g., channel 8 detects a unequipped alarm). Associated with each one the three polling bits per channel are corresponding TXC-04222-MB, Ed. 6 June 2003 DATA SHEET ...
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... AND n Alarms Mask Bits n Alarms Bit Channel n AND n Alarms Mask Bits Figure 28. Channel Polling Alarms - 57 of 246 - TEMx28 TXC-04222 Channel n Polling A Drop Alarms (74H - 77H) Channel n Polling B Drop Alarms (094H - 097H) Channel n Polling Add Alarms (055H - 058H) TXC-04222-MB, Ed. 6 June 2003 ...
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... A Drop Bus Latched Alarms (062H - 0063H) Mask Bits A Drop Bus (043H - 044H) B Drop Bus Latched Alarms (082H - 083H) Mask Bits B Drop Bus (049H - 04AH) Add Bus Latched Alarms (052H) Mask Bits A Drop Bus (03DH) TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Bit OR AND Bit OR AND ...
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... Mask Bit (MGDB, Bit 4 - 005H) Global Indication Add Bus Alarms (GAB, Bit 3 - 050H) AND Mask Bit (MGAB, Bit 3 - 005H) Figure 30. Hardware Interrupt Indication DATA SHEET OR AND Control Bit HINT=1 (Bit 7 - 005H 246 - TEMx28 TXC-04222 Hardware Interrupt Indication TXC-04222-MB, Ed. 6 June 2003 ...
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... BDPAR (bit 1, 080H). Other than an alarm indication, no action is taken within the TEMx28. DBPE PDDO (bit 0, 019H) (bit 1, 019H TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Drop Bus Parity Selection 0 Odd parity is calculated for the input leads consisting of data (A/BD(7-0)), clock (A/BDCLK), C1, J1, and V1 marker pulses (A/BDC1J1V1), and the payload indica- tion (A/BDSPE). ...
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... A side and for the B side drop buses. Each STS-1 may have its own phase regarding the H4 multiframe sequence. DATA SHEET H4 (XXXX XX00 Previous SPE 35 Bytes H4 (XXXX XX01 Bytes H4 (XXXX XX10 Bytes H4 (XXXX XX11 Bytes - 61 of 246 - TEMx28 TXC-04222 TU-11/VT1 Bytes V2 26 Bytes V3 26 Bytes V4 26 Bytes TXC-04222-MB, Ed. 6 June 2003 ...
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... When the E1n bytes are monitored for an upstream AIS condition majority logic is used to determine if an E1n byte is carrying an upstream AIS indication. If five or more ones are detected in an A/B Drop bus E1n byte, the alarm bit AxUAIS or BxUAIS is set. Recovery occurs when four or less ones are detected in the byte. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET X No upstream AIS monitoring performed ...
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... TU-12/VT2 mapping. The pointer bytes are not counted in the offset calculation. The pointer offset arrange- ment for this format is shown below. VT1.5/TU- 79-102 103 27- 53-76 77 DATA SHEET Pointer Bytes Bit Assignment VT2/TU-12 TU/VT Pointer Offset Locations - 63 of 246 - TEMx28 TXC-04222 V2 Byte 105 106-138 139 36- 71-103 104 TXC-04222-MB, Ed. 6 June 2003 ...
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... The Wrong Size Indication (A/BnSIZE) is provided by bit 0 of registers X+111/X+191H. The Positive Justification Counter is located in registers X+120H for the A side and X+1A0H for the B side. The Negative Justification Counter is located in registers X+121H for the A side and X+1A1H for the B side. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET ...
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... Inc_ind/dec_ind causes the active offset value to be incremented/decremented, respectively. The subsequent detection new_point with an offset value equal to the offset value caused by inc_ind/dec_ind will not cause the new pointer flag to assert. 13. SS-bits match for DS1 is 11 and 10 for E1. DATA SHEET Definition - 65 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... K4 byte are either 01 or 10, the RDI indication is also influenced by bit 8 in the V5 byte, as shown in the table below. When bits 6 and 7 are either 00 or 11, then RDI is determined solely by bit 8 in the TXC-04222-MB, Ed. 6 June 2003 DATA SHEET ...
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... Remote defect indication (single bit RDI Remote Server Defect; indicates Loss of Pointer - VT AIS detected - Upstream AIS detected (E1 or H1/H2 Bytes Remote Connectivity Defect - Unequipped Signal Label - J2 Mismatch - J2 Loss of Lock 1 1 Remote defect indication (single bit RDI 246 - TEMx28 TXC-04222 Definition TXC-04222-MB, Ed. 6 June 2003 ...
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... ARnJ2S0 (bit 1, X+010H) (bit 0, X+010H) BRnJ2S1 BRnJ2S0 (bit 1, X+080H) (bit 0, X+080H TXC-04222-MB, Ed. 6 June 2003 DATA SHEET AnRDIS BnRDIS Action 1 Remote Server Defect Indication, and a single bit RDI indication (Bit 8 in the V5 byte). 0 Remote Payload Defect Indication. 0 Remote Connectivity Indication. RDI Alarm Definitions ...
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... Receiving an ASCII CR/LF will synchronize an internal counter so that the next character after the last LF character will be written into the starting address of the 64 byte segment. The J2 alarms are disabled 16-Byte J2 Message ITU-T 16-Byte J2 Message Format - 69 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... OEI) in the N2 (Z6) byte. An OEI indication (a 1) indicates that the distant end has detected one or two errors when the BIP-2 calculated for frame f-1 is compared against the BIP-2 value carried in the V5 byte in frame f. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET ...
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... Note that bits 1 and 2 of the N2 (Z6) byte are masked (shown as X) and do not affect the detection. The XX represents a don’t care value and may be equal to a BIP-2 value. DATA SHEET N2 Byte Definition - 71 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... The VT/TU interface is enabled when control bits RnLINT1 (bit 7, X+006H) and RnLINT0 (bit 6, X+006H) are set to 11. The options associated with this interface are given in the following table. RnSEL RnVTVC (bit 2, X+006H) (bit 4, X+008H TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Other Bytes J2 Byte C2 O(1) O(2) O(3) 24 Bytes - Information N2 Byte C2 O(5) ...
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... TC AIS Detected (AnTCAIS, BnTCAIS), TC enabled and TCAISE Control bit RnSAIS FIFO alarm (AnRFFE, BnRFFE) - When control bit RnAISE Control bit RnSAIS Note: The AIS will be sent for two to three multiframes when a receive FIFO error occurs. DATA SHEET Operation - 73 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
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... The transmit interface selection is independent of the receive interface selection. TnLINT1 TnLINT0 (bit 7, X+002H) (bit 6, X+002H TXC-04222-MB, Ed. 6 June 2003 DATA SHEET RnOUTL (bit 5, X+006H) 0 All interface leads forced to the high impedance state. 1 All interface leads forced to the 0 state. X NRZ Interface selected. X Rail Interface selected. X VT/TU Interface selected ...
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... EXnLOSP the sense is active high. External violations TCLKn edge occurs. TCLKn edge selection is done with control bit TnCLKI DATA SHEET Interface Rate Selected Overhead Byte Access are counted when TLOSn is high and the selected . - 75 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 76
... When control bit TnSAIS When control bit TnAISE When control bit TnSAIS Note: When control bit TnAISE and the Transmit Loss of Clock (TnLOC) alarm occurs, transmit line AIS may be generated regardless of the state of control bit TnSAIS. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET - 76 of 246 - ...
Page 77
... V5 byte is transmitted DATA SHEET Operation DS1 Asynchronous format mapped to a VT1.5/TU-11. Not used. Cross Mapping. DS1 Asynchronous format mapped to a VT2/TU-12. E1 Asynchronous format mapped to a VT2/TU-12 REI RFI Signal Label - 77 of 246 - TEMx28 TXC-04222 RDI LSB TXC-04222-MB, Ed. 6 June 2003 ...
Page 78
... Unequipped (AnUNEQ, BnUNEQ), when UQRDIE Loss of Lock (AnJ2LOL, BnJ2LOL), when J2RDIE Mismatch (AnJ2TIM, BnJ2TIM), when J2RDIE Microprocessor writes ATnRDIS, BTnRDIS - When RDI enable (RnDIEN Microprocessor writes ATnRDIS, BTnRDIS TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Definition No defect indications. Remote Defect Indication - 78 of 246 - ...
Page 79
... No defect indications. 0 Single bit Remote Defect Indication 1 Remote Server Defect - VT Loss of Pointer - VT AIS detected - Upstream AIS detected (E1 or H1/H2 Bytes). 0 Remote Connectivity Defect - Unequipped Signal Label - J2 Mismatch - J2 Loss of Lock. 1 Single bit Remote Defect Indication 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 80
... X+061H (A side N2 byte) for the A side, and X+0D1H (B side N2 byte) for the B side is repeated 16 times as the trail trace message. The bit placement of the transmitted N2 (Z6) byte is as shown below: Bit 1 2 BIP-2 MSB TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Operation Operation ...
Page 81
... VT AIS detected (AnVCAIS, BnVCAIS) when VCTCE Loss Of Multiframe (AnTCLM, BnTCLM Loss Of Lock Alarm (AnTCLL, BnTCLL Mismatch Alarm (AnTCTM, BnTCTM Unequipped Alarm (AnTCUQ, BnTCUQ written to ATnTCSR, BTnTCSR - When TC enable (TCnRE written to ATnTCSR, BTnTCSR DATA SHEET N2 Byte Definition - 81 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 82
... ATnGAIS (bit 6, X+063H) or BTnGAIS (bit 6, X+0D3H) for channel n, a TU/VT AIS is generated for corresponding bus. A TU/VT AIS consists of all ones in the entire tributary signal, including bytes V1 through V4. A TU/VT AIS will override a unequipped channel when set. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET ...
Page 83
... X+0D3H) (bit 3, X+0D3H Note: Control bits ATnTPTV (bit 5, X+063H) and BTnTPTV (bit 5, X+0D3H) must be set to 0 when generating unequipped or supervisory unequipped. DATA SHEET X Normal Operation. 0 Unequipped TU/VT Generated 1 Unequipped Supervisory TU/VT Generated - 83 of 246 - TEMx28 TXC-04222 Action TXC-04222-MB, Ed. 6 June 2003 ...
Page 84
... The two add buses, A and B, consists of leads supporting the COMBUS interface. The possible interface selections, including bus timing, are according to the following table. ABUST ABTE Low High High TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Add Bus Interfaces X Add Bus Timing Mode. The output leads consists of data (A/BA(7-0)), parity, (A/BAPAR), and Add indicator (A/BADD) ...
Page 85
... C1, J1, and V1 marker pulses (A/BAC1J1V1), and payload indica- tion (A/BASPE) when they are provided as outputs in the drop bus timing mode. 1 Even parity is calculated for the data output leads (A/BA(7-0)). - 85 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 86
... Facility loopback enables the transmit DS1 or E1 data and clock signals to be looped back as the receive Data and Clock signals. The transmit data is sent for the VT/TU selected. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET 15 -1 pattern for more then 25 clock cycles. ...
Page 87
... RnAISE “1” PRBS 1 Analyzer 0 PRBS 1 Generator Line Loopback PRBSA LnLBK “1” TnAISE “1” TnSAIS - 87 of 246 - TEMx28 TXC-04222 RnLAIS (Only when LnLBK=1) Rx “1” T1/E1 0 Line 1 FnLBK Facility Loopback 1 Tx T1/E1 0 Line PRBSG TnTPG TXC-04222-MB, Ed. 6 June 2003 ...
Page 88
... On the transmit side (T1/E1 to SONET/SDH) the nominal delay for T1 is approximately 64 s and for E1 is approximately 42 s. The nominal conditions for the transmit side are the same as for the receive side. B8ZS and HDB3 line coding also add the same delay. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET ...
Page 89
... D = Absolute Value [sum 27+i 30+i )], G = Absolute Value [S ] and i represents the number of times through the 30+i 30 246 - TEMx28 TXC-04222 Calculate 30 SEC FIFO Leak Rate (Note 5) Set FIFO Leak Rate (Note 6) Measure 1 Second (Note 6) )], E = Absolute Value [sum 28+i TXC-04222-MB, Ed. 6 June 2003 )], 30+i ...
Page 90
... Frequency 100 Hz F2 500 Hz 1 kHz F3 8 kHz 25 kHz F4 40 kHz Figure 35. DS1 (1544 kbit/s) Jitter Tolerance TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Requirement Maximum Input Jitter Tolerated (UI-PP) >1.5 UI > 1.5 UI > 0.2 UI > 0.2 UI Requirement Maximum Input Jitter (UI pp) (UI pp) > ...
Page 91
... Input Jitter Frequency (Hz) Figure 36. Jitter Tolerance Measurements DATA SHEET Receiver E1/DS1 Interface Transmitter Maximum Tolerated Input Jitter Minimum Requirement 10000 100000 Maximum Tolerated Input Jitter Minimum Requirement 10000 100000 - 91 of 246 - TEMx28 TXC-04222 PDH Digital Transmission Analyzer TXC-04222-MB, Ed. 6 June 2003 ...
Page 92
... The jitter value measured is achieved using the HP1/LP filter in the PDH receiver. The jitter transfer measurements are provided in the following table and figure. TEMx28 Test Fixture Input Jitter Frequency 100 Hz 250 Hz 500 Hz 1000 Hz TXC-04222-MB, Ed. 6 June 2003 DATA SHEET HP-3784A Digital Transmission Analyzer Filter Used Jitter Transfer (UI - PP, Max) Unit Interval E1 Rate 1.0 UI ...
Page 93
... Input Jitter Frequency (Hz) Figure 37. E1 Jitter Transfer Measurements Jitter Transfer - DS1 Rate 10 1 0.1 0.01 10 100 0.001 Input Jitter Frequency (Hz) Figure 38. DS1 Jitter Transfer Measurements DATA SHEET 1000 1000 - 93 of 246 - TEMx28 TXC-04222 Input Measured Output Input Measured Output TXC-04222-MB, Ed. 6 June 2003 ...
Page 94
... Note 1:These values are for further study. Interface DS1 - 1544 kbit/s Notes: 1. Per Recommendation ITU-T G.783 (04/97). 2. Per Bellcore GR-253-CORE Issue 2 Dec. 95: Rev 2 Jan. 99. 3. These values are for further study. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET TEMx28 Interface SONET Data Test Fixture ...
Page 95
... Leak Rate (Hex) (Note 1) Requirement f1-f4 52H (HP1/LP) (Note 2) 52H 52H f3-f4 52H (HP2/LP) (Note 2) 52H 52H - 95 of 246 - TEMx28 TXC-04222 Anritsu MP 1560A Analyzer Maximum Output Jitter (UI - PP) Measured 0.4 0.240 0.176 0.187 0.075 0.010 0.010 0.010 TXC-04222-MB, Ed. 6 June 2003 ...
Page 96
... Proprietary TranSwitch Corporation Information for use Solely by its Customers TEMx28 TXC-04222 Figure 39. TU-12 Standard Pointer Test Sequences Single P ointers of Opposite Polarity Regular Pointers plus one Double Poiner Regular Pointers with one Missing Value TXC-04222-MB, Ed. 6 June 2003 DATA SHEET (Ref: ITU-T G.783, F ig. 6- 246 - T3 ...
Page 97
... Leak Rate Filter Value (Hex) (Note 3) G.783 (Note 1) (f4) 3FFH 25H 19H 7DH 246 - TEMx28 TXC-04222 Maximum Output Jitter (UI pp) Requirement Measured Bellcore (Note 2) 1 0.60 0.119 (Note 4) 1.5 1.3 0.222 1.5 1.3 0.600 1.5 1.9 0.218 TXC-04222-MB, Ed. 6 June 2003 ...
Page 98
... Pointer Adjustment Periodic VT1.5 Pointer Adjustment Test Sequence (26-1 Pattern) Pointer Adjustment Periodic VT1.5 Pointer Adjustment Test Sequence (Continuous Pattern) Periodic VT1.5 Pointer Adjustment Test Sequence (Continuous Pattern Plus Add) TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Pointer Adjustment 30 s Measurement Period ...
Page 99
... V Output and Input/Output Parameters’ section of this Data Sheet for worst case leakage currents of all devices sharing this pull-down resistor. DATA SHEET requirements listed in the ‘Input 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 100
... Proprietary TranSwitch Corporation Information for use Solely by its Customers TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Boundary Scan Register CORE LOGIC OF TEMx28 DEVICE Instruction Register Bypass Register TAP Controller 3 TDI TDO Controls IN OUT Boundary Scan Serial Test Data Figure 41. Boundary Scan Schematic ...
Page 101
... A5 tni26 B6 tclk26 * ‘1’ drives tclk26 to ‘Z’ C7 tpi26 D8 rno26 A6 rclk26 B7 rpo26 * ‘1’ drives rno26, rclk26, rpo26 to ‘Z’ C8 tni25 D9 tclk25 * ‘1’ drives tclk25 to ‘Z’ - 101 of 246 - TEMx28 TXC-04222 Comments TXC-04222-MB, Ed. 6 June 2003 ...
Page 102
... TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Symbol A7 tpi25 B8 rno25 A8 rclk25 C9 rpo25 * ‘1’ drives rno25, rclk25, rpo25 to ‘Z’ D10 tni24 B9 tclk24 * ‘1’ drives tclk24 to ‘Z’ C10 tpi24 ...
Page 103
... TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 104
... TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Symbol C19 tclk17 * ‘1’ drives tclk17 to ‘Z’ B21 tpi17 D20 rno17 C21 rclk17 E19 rpo17 * ‘1’ drives rno17, rclk17, rpo17 to ‘Z’ ...
Page 105
... TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 106
... TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Symbol * ‘1’ drives rno10, rclk10, rpo10 to ‘Z’ R22 tni9 R21 tclk9 * ‘1’ drives tclk9 to ‘Z’ T22 tpi9 ...
Page 107
... TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 108
... TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Symbol AB15 rclk2 Y14 rpo2 * ‘1’ drives rno2, rclk2, rpo2 to ‘Z’ W13 tni1 AA14 tclk1 * ‘1’ drives tclk1 to ‘Z’ ...
Page 109
... TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 110
... TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Symbol T2 tvtf15 R3 aadd P4 aaclk T1 aapar R2 aaspe R1 aac1j1v1 * ‘1’ drives aac1j1v1,aaspe,aaclk to ‘Z’ P3 aa(0) N4 ...
Page 111
... Symbol Comments ba(7) * ‘1’ drives ba(7:0), bapar to ‘Z’ adpar adspe adc1j1v1 ad(0) ad(1) ad(2) ad(3) ad(4) ad(5) ad(6) ad(7) bdpar bdclk bdspe bdc1j1v1 bd(0) bd(1) bd(2) bd(3) bd(4) bd(5) bd(6) bd(7) - 111 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 112
... Please note: the mapper does not insert the overhead bytes into the STS-1. VT1.5 3 COLUMNS BYTES 1.5 1.5 1.5 1.5 1 Note: Columns 88, 89, 90, 175, 176 and 177 are fixed stuff. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET 1.5 1.5 1 STS-3/AU-3 SPE - 112 of 246 - ...
Page 113
... STS-1 #3, AU-3 C TXC-04222-MB, Ed. 6 June 2003 ...
Page 114
... The following diagram and table illustrate the mapping of the 63 VT2/TU-12s into an STS-3/AU-3 SPE. Each STS-3 carries three STS-1s. Column 1 in each STS-1/AU-3 is assigned to carry the path overhead bytes. VT2 4 COLUMNS BYTES Note: Columns 88, 89, 90, 175, 176 and 177 are fixed stuff. TXC-04222-MB, Ed. 6 June 2003 DATA SHEET STS-3/AU-3 SPE - 114 of 246 - ...
Page 115
... STS-1 #3, AU-3 C TXC-04222-MB, Ed. 6 June 2003 ...
Page 116
... The following diagram and table illustrate the mapping of the 84 TU-11s into an STM-1/VC-4. The TEMx28 permits the mapping line signals into any of the 84 available time slots when the VC-4 is config- ured to carry TU-11s. 3 COLUMNS TUG TUG VC TXC-04222-MB, Ed. 6 June 2003 DATA SHEET TU- STM-1/VC-4 - 116 of 246 - ...
Page 117
... TUG-3 C TXC-04222-MB, Ed. 6 June 2003 ...
Page 118
... The following diagram and table illustrate the mapping of the 63 TU-12s into an STM-1/VC-4. The TEMx28 permits the mapping line signals into any of the 63 available time slots when the VC-4 is config- ured to carry TU-12s. 4 COLUMNS TUG VC TXC-04222-MB, Ed. 6 June 2003 DATA SHEET 4 TU- TUG-3A TUG-3B STM-1/VC-4 - 118 of 246 - ...
Page 119
... TXC-04222-MB, Ed. 6 June 2003 ...
Page 120
... R 1 001 R 1 002 R 0 003 R Revision (Version) Level 004 R COMMON CONTROL REGISTERS - A and B SIDES Address Status Bit 7 (Hex) 006 R/W TXC-04222-MB, Ed. 6 June 2003 DATA SHEET R=Read; R(L)=Read (Latched); R/W=Read/Write; or Bit 6 Bit 5 Bit 4 Bit Set to 0000 Bit 6 Bit 5 Bit 4 ...
Page 121
... DLCAE TCUAE TCAISE UQTCE USTCE J2RDIE UQRDIE URDIE DRESET BAHZE AAHZE ADDI TB2DIS ABOD THRSBY TRESET Bit 2 Bit 1 Bit 0 MPCDA MPCDB MPCAB MDRFI MDLOP MDNDF MDSIZE MTLOC MDJ2TIM MDJ2LOL MTCRDI MTCODI MBBLOC MABLOC Add Alarm Mask Bits TXC-04222-MB, Ed. 6 June 2003 ...
Page 122
... Channel Polling Register (Channels 8-1) A Bus Drop Alarm Mask Bits 046 R/W Channel Polling Register (Channels 16-9) A Bus Drop Alarm Mask Bits 047 R/W Channel Polling Register (Channels 24-17) A Bus Drop Alarm Mask Bits 048 R/W TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 GDA GDB ...
Page 123
... A Side Drop Bus E1 Overhead Byte (STS-3 STS-1 No. 3) Reserved A Side Drop Channel Polling Register Reserved - 123 of 246 - TEMx28 TXC-04222 Bit 2 Bit 1 Bit 0 A1UAIS ADPAR ADLOC A3HLOM A2HLOM A1HLOM LA1UAIS LADPAR LADLOC PA1UAIS PADPAR PADLOC FA1UAIS FADPAR FADLOC (Channels 28-25) Alarm Bits TXC-04222-MB, Ed. 6 June 2003 ...
Page 124
... Channel Polling Register (Channels 16-9) B Bus Drop Alarm Mask Bits 04D R/W Channel Polling Register (Channels 24-17) B Bus Drop Alarm Mask Bits 04E R/W 04F R TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 MB3UAIS MB2UAIS MB1UAIS MBDPAR MBDLOC MB3OOM MB2OOM MB1OOM MB3LOM MB2LOM MB1LOM ...
Page 125
... B Side Drop Bus E1 Overhead Byte (STS-3 STS-1 No. 3) Reserved B Side Drop Channel Polling Register Reserved - 125 of 246 - TEMx28 TXC-04222 Bit 2 Bit 1 Bit 0 B1UAIS BDPAR BDLOC B3HLOM B2HLOM B1HLOM LB1UAIS LBDPAR LBDLOC PB1UAIS PBDPAR PBDLOC FB1UAIS FBDPAR FBDLOC (Channels 28-25) Alarm Bits TXC-04222-MB, Ed. 6 June 2003 ...
Page 126
... R/W TnLINT1-0 X+003 R/W X+004 R/W X+006 R/W RnLINT1-0 X+007 R/W X+008 R/W X+009 R/W X+00A R to X+00F TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 RnNRZP RnCLKI Reserved TnNRZP TnE1SL TnCLKI TnPTG TnANZ RnOUTL RnE1SL FnRDIS RnVTVC RnDIEN ...
Page 127
... Bit 4 Bit 3 Pointer Leak Value (Bit 7-0) Reserved - 127 of 246 - TEMx28 TXC-04222 Bit 2 Bit 1 Bit 0 ARnJ2S1 ARnJ2S0 DACHnR ATnTCEN ATnJ2TEN ATnJ2TSZ ATnT- ATnV5BS CUQ ATnK4PC AnHIGHZ ATnTCSO ATnTCSR ATnV4BS Bit 2 Bit 1 Bit 0 Pointer Leak Value (Bit 9-8) TXC-04222-MB, Ed. 6 June 2003 ...
Page 128
... X+0FF CHANNEL SIDE DROP POINTER LEAK REGISTERS ( 28) Address Status Bit 7 (Hex) X+087 R/W X+088 R/W X+089 R TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 BRnTCEN BRnSL(1-3) B Side Drop Bus Channel n VT/TU Selection B Side Add Bus Channel n VT/TU Selection Reserved ...
Page 129
... FTBnFFE FTAnFFE FCnOOL Code Violation Counter - Low Order Byte (7-0) Code Violation Counter - Low Order Byte (15-8) Reserved - 129 of 246 - TEMx28 TXC-04222 Bit 2 Bit 1 Bit 0 MnOOL MnTLOS MnTLOC Bit 2 Bit 1 Bit 0 CnOOL TnLOS TnLOC LTnLOS LTnLOC PTnLOC FTnLOS FTnLOC TXC-04222-MB, Ed. 6 June 2003 ...
Page 130
... FAnVCAIS FAnUNEQ X+11D R X+11E R X+11F R FAnTCLM FAnTCLL FAnTCT CHANNEL SIDE DROP COUNTERS ( 28) Address Status Bit 7 (Hex) X+120 R/W X+121 R/W TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 MAnRFE MAnAIS ManTCTM MAnTCAIS MAnTCUQ Bit 6 Bit 5 Bit 4 Bit 3 AnRDIC AnRDIP AnRFFE ...
Page 131
... A Side BIP-2 (V5 byte) Counter for Channel bits A Side TC OEI (N2 byte) Counter for Channel bits A Side TC REI (N2 byte) Counter for Channel bits A Side TC BIP-2 (N2 byte) Counter for Channel bits Reserved Reserved Reserved - 131 of 246 - TEMx28 TXC-04222 Bit 2 Bit 1 Bit 0 TXC-04222-MB, Ed. 6 June 2003 ...
Page 132
... R X+187 R X+188 R X+189 R X+18A R X+18B TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 A Side Drop Bus Channel n J2 Byte 64 Byte Message or A Side Drop Bus Channel n J2 Byte 16 Byte Message A Side Drop Bus Channel n N2 Byte 16 Byte Message ...
Page 133
... MBnLOP MBnNDF MBnSIZE MBnJ2TIM MBnJ2LOL MBnTCRDI MBnTCODI Bit 2 Bit 1 Bit 0 BnRDIS BnSLER BnRFI BnLOP BnNDF BnSIZE BnJ2TIM BnJ2LOL LBnRFI LBnLOP LBnNDF LBnSIZE LBnJ2TIM LBnJ2LOL PBnLOP PBnNDF PBnSIZE PBnJ2TIM PBnJ2LOL FBnLOP FBnNDF FBnSIZE FBnJ2TIM FBnJ2LOL Bit 2 Bit 1 Bit 0 TXC-04222-MB, Ed. 6 June 2003 ...
Page 134
... R to X+1E2 X+1E3 R/W to X+202 X+203 R X+204 R X+205 R X+206 R TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 B Side TC REI (N2 byte) Counter for Channel bits B Side TC BIP-2 (N2 byte) Counter for Channel bits Reserved Reserved Bit 6 Bit 5 Bit 4 Bit 3 B Side Drop Bus Channel n J2 Byte 64 Byte Message ...
Page 135
... DATA SHEET Bit 5 Bit 4 Bit 3 Bit 2 B Side Drop Bus Channel n J2 Byte B Side Drop Bus Channel n N2 Byte B Side Drop Bus Channel n K4 Byte B Side Drop Bus Channel n O Bits Reserved - 135 of 246 - TEMx28 TXC-04222 Bit 1 Bit 0 TXC-04222-MB, Ed. 6 June 2003 ...
Page 136
... RESETH 018 7-4 3 PRBSA 2 1 PRBSG 0 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Part Number Manufacturer Identifier 16 bits Description Not used: Reset Device: This bit is equivalent to the hardware reset. When written to this bit, the internal FIFOs and logic are reset to preset values, counters and control bits in the memory map are reset to zero ...
Page 137
... Odd parity check over drop data only Even parity check over drop data, SPE, and C1J1V1 Even parity check over drop data only. Other than reporting the event, no action is taken upon parity error indi- cation. - 137 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 138
... INTR1 6 INTR0 5-2 1 PTALTE 0 V5AL10 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: Reset All Channel Counters written to this control bit causes all performance counters to be reset to a zero value (for saturating counters) or the FE/FFFE Hex values (for 8/16-bit non-saturating counters) ...
Page 139
... H1/H2 bytes (control bit SE1AIS is 0 the E1 bytes (control bit SE1AIS is 1 disables the detection of an upstream AIS state. Note that the TU/VT pointer tracking state machine AIS detection circuitry operates independently of H1/ byte AIS detection circuits. - 139 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 140
... VCAISE 2 DLCAE 1 TCUAE 0 TCAISE TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: VC AIS Alarm Line AIS Enable: A common control for both the A and B Drop bus signal label AIS alarm (A/BnVCAIS enables a VC AIS alarm for the active bus to generate line AIS provided control bit RnAISE is set to 1 ...
Page 141
... A and B Drop bus upstream AIS alarm (A/BxUAIS enables an upstream AIS alarm for the active bus to generate a Tandem Connection RDI and ODI provided control bit TCnRE is set to 1, and the Tandem Connection feature is enabled. - 141 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 142
... UQRDIE 0 URDIE 039 7-1 0 DRESET TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: VC AIS Alarm RDI Enable: A common control for both the A and B Drop bus signal label AIS alarm (A/BnVCAIS enables a VC AIS alarm for the active bus to generate either a single bit RDI state or a Remote Server Defect Indication (three bit RDI) when control bit RnDIEN is set to 1 ...
Page 143
... In the drop bus timing mode, if the AACLK, AASPE, and AAC1J1V1 signals are enabled as outputs they will be forced to the high impedance state when this bit is set addition to the data output leads and parity lead. The Add indicator (BADD) is turned off. - 143 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 144
... ABOD 0 THRSBY 03C 7-1 0 TRESET TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Add Indicator Inversion causes the A and B Add bus output indi- cator signals (AADD and BADD active high instead of active low for all TU/VT added to the buses. Not used: Transmit Disable BIP2 Tandem Connection Unequipped dis- ables the BIP2 (in bits 1 and 2) from being transmitted in an unequipped tandem connection (N2) byte ...
Page 145
... A and B add polling registers (A and B add alarms for all channels) when control bit HINT is set disables the hardware interrupt for the global indication bit PCAB. - 145 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 146
... MDRDIP 2 MDRDIS 1 MDSLER 0 MDRFI TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: Mask Bit VC AIS Alarm A and B Drop All Channels enables a channel polling register bit for the A and B drop sides to set when a VC AIS latched alarm occurs in any channel disables a VC AIS latched alarm in any channel from setting the corresponding polling bit ...
Page 147
... Mask Bit Size Alarm A and B Drop All Channels enables a chan- nel polling register bit for the A and B drop sides to set when a VT/TU size latched alarm occurs in any channel disables a VT/TU size latched alarm in any channel from setting the corresponding polling bit. - 147 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 148
... MTLOS 2 MTLOC 1 MDJ2TIM 0 MDJ2LOL TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: Mask Bit Transmit Line AIS Alarm All Channels enables a chan- nel polling register bit for the A and B add sides to set when a transmit line AIS latched alarm occurs in any channel disables a transmit line AIS label latched alarm in any channel from setting the corresponding polling bit ...
Page 149
... A/B side add alarm in the corresponding channel to set the global indication (PCAB) bit disables the channel corre- sponding to a polling bit from setting the global indication (PCAB) bit. Bit 7 is the mask bit for channel 8 add side alarms. - 149 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 150
... GDA 4 GDB 3 GAB TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Mask Bits Polling Registers Channels 16-9 Add Alarms one or more bits enables an A/B side add alarm in the corresponding chan- nel to set the global indication (PCAB) bit disables the channel cor- responding to a polling bit from setting the global indication (PCAB) bit ...
Page 151
... An alarm occurs when the input add clock is stuck high or low for 56 clock cycles of DSCLK. Recovery to 0 occurs on the first clock transition. - 151 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 152
... Polling Register Add Alarms Channels 16-9 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: B Add Bus Loss Of Clock Alarm Latched Alarm Indication: This bit position latches when the B side Add bus has detected a loss of clock when add bus timing is selected. This bit is set on either a positive transi- tion, negative transition or positive and negative transition ...
Page 153
... Micropro- cessor access of the TEMx28 is not valid until this bit is set to 1. This bit goes to zero immediately after the hardware or software reset has been invoked. - 153 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 154
... MA2UAIS 2 MA1UAIS 1 MADPAR 0 MADLOC TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not Used: Mask Bit for Global Indication for Upstresm AIS indication for A Drop Bus STS-3 STS-1 No.3/STM-1 AU enables the global indication (GDA set for an upstream AIS indication that has been detected in the H1/H2 bytes or in the E1 byte for STS-3 STS-1 No ...
Page 155
... A drop side alarm in the corresponding channel to set the global indication (PCDA) bit disables the channel corresponding to a polling bit from setting the global indication (PCDA) bit. Bit 7 is the mask bit for channel 16 A drop side alarms. - 155 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 156
... Mask Bits A Drop Polling Register Channel 28-25 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Mask Bits Polling Registers Channels 24-17 A Drop Alarms one or more bits enables an A drop side alarm in the corresponding channel to set the global indication (PCDA) bit disables the channel corresponding to a polling bit from setting the global indication (PCDA) bit ...
Page 157
... A Side Drop Bus Loss Of Clock Unlatched Alarm Indication indicates that the A side Drop bus has detected a loss of clock. An alarm occurs when the input drop clock is stuck high or low for 56 clock cycles (DSCLK clock). Recovery occurs on the first clock transition. - 157 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 158
... A1HOOM 2 A3HLOM 1 A2HLOM 0 A1HLOM TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: A Side Drop Bus H4 Byte Out Of Multiframe Alignment (Unlatched) Alarm - STS-3 STS-1 No. 3/AU-3 C: Enabled when control bit DV1SEL Out Of Multiframe alarm for STS-3 STS-1 No. 3/AU declared once an error is detected in the bit 7 and 8 sequence in the H4 byte ...
Page 159
... A Side Drop Bus Loss Of Clock Latched Alarm Indication: This bit position latches for the A side loss of clock alarm. This bit is set on either a positive transition, negative transition or positive and negative alarm transition. This bit is cleared on a read cycle. - 159 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 160
... LA1HOOM A Side Drop Bus H4 Byte Out Of Multiframe Alignment Latched 2 LA3HLOM 1 LA2HLOM 0 LA1HLOM TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: Alarm Indication - STS-3 STS-1 No. 3/AU-3 C: This bit position latches for the A side STS-3 STS-1 No. 3/AU byte Out of Multiframe alarm. This bit is set on either a positive transition, negative transition or positive and negative alarm transition ...
Page 161
... A side loss of clock alarm indication has changed state in the last one second interval the end of the interval. This bit is disabled if the one second pulse is not applied. This indication does not cause an interrupt. - 161 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 162
... PA1HOOM A Side Drop Bus H4 Byte Out Of Multiframe Alignment One Second 2 PA3HLOM 1 PA2HLOM 0 PA1HLOM TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: Alarm Indication - STS-3 STS-1 No. 3/AU-3 C: This bit position is set when the A side STS-3 STS-1 No. 3/AU byte Out Of Multiframe Alignment alarm indication has changed state in the last one second interval the end of the interval ...
Page 163
... A Side Drop Bus Loss Of Clock Persistent One Second Alarm Indi- cation: This bit position is set to 1 for the one-second interval, when the A side loss of clock alarm indication is active, but did not become active in the previous one second interval. - 163 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 164
... Drop Bus H1 Byte 069 7-0 A Side Drop Bus H1 Byte TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: One Second Alarm Indication - STS-3 STS-1 No. 3/AU-3 C: This bit position is set to 1 for the one-second interval, when the A side STS-3 STS-1 No. 3/AU byte Out Of Multiframe alarm indication is active, but did not become active in the previous one second interval ...
Page 165
... A Side Drop Bus E12 Overhead Byte for STS-3 STS-1 No. 2/AU-3 B: The value in this location is dropped E1 overhead byte in the A Drop Bus STS-3 STS-1 No. 2/AU-3 B format. This register location is updated every 125 microseconds. Bits 7-0 of the register correspond to bits 1-8 of the E1 byte. - 165 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 166
... A Side Drop Polling Bits Channels 28-25 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description A Side Drop Bus E1 Overhead Byte for STS-3 STS-1 No. 3/AU-3 C: The value in this location is dropped E1 overhead byte in the A Drop Bus STS-3 STS-1 No. 3/AU-3 C format. This register location is updated every 125 microseconds ...
Page 167
... Mask Bit for Global Indication for B Drop Loss of Clock Alarm enables the global indication (GDB set for a loss of clock alarm detected for the B side drop bus disables the global indication bit GDB for this alarm. - 167 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 168
... Mask Bits B Drop Polling Register Channel 24-17 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: Mask Bit for Global Indication for H4 Out Of Multiframe Indication for B Drop Bus STS-3 STS-1 No.3/STM-1 AU enables the glo- bal indication (GDB set for an H4 Out Of Multiframe indication for STS-3 STS-1 No ...
Page 169
... B side drop alarm in the corresponding channel to set the global indication (PCDB) bit disables the channel corre- sponding to a polling bit from setting the global indication (PCDB) bit. Bit 3 is the mask bit for channel 28 B drop side alarms. - 169 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 170
... B2UAIS 2 B1UAIS 1 BDPAR 0 BDLOC TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: B Side Drop Bus Upstream AIS (Unlatched) Alarm Indication - STS-3 STS-1 No. 3/AU indicates that AIS has been detected on the B side drop bus in the H1/H2 bytes or in the E13 byte for the STS-3 STS-1 No ...
Page 171
... Recovery will occur when the multiframe is recovered. The Loss of Multiframe alarm forces a VT/TU Loss of Pointer alarm (BnLOP) for all channels which have a VT/TU selected for STS-3 STS-1 No. 1/AU-3 A, STM-1 VC-4. - 171 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 172
... LB2UAIS 2 LB1UAIS 1 LBDPAR 0 LBDLOC TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: B Side Drop Bus Upstream AIS Latched Alarm Indication - STS-3 STS-1 No. 3/AU-3 C: This bit position latches for the B side received upstream AIS alarm Indication for the STS-3 STS-1 No. 3/AU-3 C for- mat ...
Page 173
... B side STS-3 STS-1 No. 1/AU STM-1 VC-4 H4 byte Loss of Multiframe alarm. This bit is set on either a positive transi- tion, negative transition or positive and negative alarm transition. This bit is cleared on a read cycle. - 173 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 174
... PB2UAIS 2 PB1UAIS 1 PBDPAR 0 PBDLOC TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: B Side Drop Bus Upstream AIS One Second Alarm Indication - STS-3 STS-1 No. 3/AU-3 C: This bit position is set when the B side received upstream AIS alarm Indication - STS-3 STS-1 No. 3/AU-3 C has changed state in the last one second interval the end of the interval ...
Page 175
... STM-1 VC-4 H4 byte Loss Of Multiframe Alignment alarm indication has changed state in the last one second interval the end of the interval. This bit is disabled if the one second pulse is not applied. This indication does not cause an interrupt. - 175 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 176
... FB2UAIS 2 FB1UAIS 1 FBDPAR 0 FBDLOC TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: B Side Drop Bus Upstream AIS Persistent One Second Alarm Indi- cation - STS-3 STS-1 No. 3/AU-3 C: This bit position is set to 1 for the one-second interval, when the B side received upstream AIS alarm Indi- cation - STS-3 STS-1 No ...
Page 177
... B Side Drop Bus H1 Pointer Byte for STS-3 STS-1 No. 2/AU-3 B: The value in this location is dropped H1 Pointer byte in the B Drop Bus STS-3 STS-1 No. 2/AU-3 B format. This register location is updated every 125 microseconds. Bits 7-0 of the register correspond to bits 1-8 of the H1 byte. - 177 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 178
... E1 Byte 092 7-0 B Side Drop Bus E1 Byte TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description B Side Drop Bus H1 Pointer Byte for STS-3 STS-1 No. 3/AU-3 C: The value in this location is dropped H1 Pointer byte in the B Drop Bus STS-3 STS-1 No. 3/AU-3 C format. This register location is updated every 125 microseconds ...
Page 179
... This bit is cleared when the B side latched alarms corre- sponding to the channel that is set to 1 are read, or the mask bit associ- ated with the alarm in the interrupt hierarchy is set 179 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 180
... RnCLKI 2 RnB8ZS 1 0 RnLAIS X+001 7-0 TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: Receive Data Invert Enable for NRZ Data inverts the receive NRZ data stream when the NRZ interface is selected enables normal oper- ation. Not used: Receive Clock Invert Enable: Valid for all interfaces. When this control bit is set to 1, data and any other line signals, shall be clocked out on pos- itive transitions of the clock ...
Page 181
... Transmit Loss Of Clock alarm (TnLOC) - Transmit Loss Of Signal alarm (TnLOS) when the rail interface is selected - External Loss Of Signal alarm (TnLOS) when NRZ interface is selected and control bit EXnLOS Control bit TnSAIS Control bit TnSAIS 181 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 182
... TnPRN 1 LnLBK 0 FnLBK TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: Transmit External Loss Of Signal Enable: Enabled only when the trans- mit NRZ interface is selected configures the negative rail interface lead for an external loss of signal indication configures the negative rail interface lead for external coding violations ...
Page 183
... A Drop only (Drop Drop only (Drop Drop A Add (Single Unidirectional Ring Drop B Add (Single Unidirectional Ring Drop B Add (Multiplexer Drop A Add (Multiplexer Drop A and B Add (Dual Unidirectional Ring Drop B and A Add (Dual Unidirectional Ring) - 183 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 184
... RnAISE 0 RnSAIS X+009 7-1 0 TnRESET TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: Receive VT/TU Overhead Byte Selection: Enabled with the VT/TU receive line interface is selected causes the output clock RVTCn to be gapped during the four overhead byte times causes the clock to be symmetrical, and enables the four overhead bytes to be clocked out of the mapper ...
Page 185
... FE/FFFE hex values (8/16 bit non-saturating), and initializes the internal FIFOs and state machines for the A drop bus VT/TU channel selected. It does not clear the control bit settings, or latched alarms for the channel selected. - 185 of 246 - TEMx28 TXC-04222 Action TXC-04222-MB, Ed. 6 June 2003 ...
Page 186
... O-bits X+060 7-0 A Side Add Bus V5 Byte TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description A Side Drop Channel n VT/TU Selection: The eight-bit binary code writ- ten into this location selects the TU/VT that dropped from the A side drop bus. Please refer to the operations section for the description for selecting a VT/TU for a STS-1 in the STS-3 format, and for a TUG-3 in the STM-1 VC-4 format ...
Page 187
... A 1 enables the test pointer value written to registers X+05CH (V1 byte) and X+05DH (V2 byte) by the microprocessor to be transmitted. Please note that the pointer offset for the overhead bytes (e.g., V5 byte) and the payload will remain fixed. DATA SHEET Description - 187 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 188
... Address Bit Symbol X+063 4 AnUQGE (cont.) 3 AnUQSU 2 ATnTCEN TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description A Side Add Bus Channel n Unequipped Channel Generation: This control bit works in conjunction with the AnUQSU control bit according to the following table: AnUQGE AnUQSU Action 0 X Normal Operation. ...
Page 189
... V5 byte value at register X+060H to be transmitted. DATA SHEET Description Action 0 0 Transmit J2 message segment configured for a 16-byte message size Transmit J2 message segment configured for a 64-byte message size message segment transmitted as 00H. - 189 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 190
... ATnTCSO 1 ATnTCSR 0 ATnV4BS TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: A Side Add Bus Channel n Transmit REI Error causes bit 3 (REI) of the V5 byte to be transmitted for one multiframe. To send another error, this bit must be written with a 0 followed Please note that if a FEBE is being sent as a result of a receive BIP-2 error, the REI error set by this bit is transmitted afterwards ...
Page 191
... A count of one represents 8 frames multi- frames, between bits leaked. Bit 9 is the MSB. Note: If the 10 bit register is set to 0 the pointer leak buffer in the Desyn- chronizer is bypassed. - 191 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 192
... BRnJ2S1 BRnJ2S0 X+081 7-1 0 DBCHnR TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Not used: B Side Drop Bus Channel n Tandem Connection Enable enables the B side drop bus Tandem Connection feature for the VT/TU selected for channel disables the TC feature. Please note the Tandem Connec- tion feature can only be enabled when the J2 byte is configured for a 16 byte message ...
Page 193
... BTnV5BS is set normal V5 byte is transmitted. Bits 7-0 of the register correspond to bits 1-8 of the V5 byte. DATA SHEET Description Message Segment Transmit J2 message segment (64 bytes). Transmit J2 message segment (16 bytes). Unused (16 bytes). Transmit N2 message segment (16 bytes). Unused (16 bytes). - 193 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 194
... BTnTCAIS 6 BTnGAIS 5 BTnTPTV TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description B side Add Bus Channel n N2 byte: The value written to this location is transmitted as the N2 byte for the VT/TU selected for the B side add bus and when control bit ATnTCEN (bit 2, register X+0D3H Bits 7-0 of the register correspond to bits 1-8 of the N2 byte ...
Page 195
... The J2 message segment is configured for a 64 message size. The single byte microprocessor written value is repeated and transmitted 16 times along with the multiframe alignment pat- tern, and TC ODI and TC RDI. - 195 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 196
... BTnRDIC 4 BTnRDIS 3 BTnFB2 2 BTnTCUQ 1 0 BTnV5BS TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description B Side Add Bus Channel n Transmit J2 Message Type: Works in con- junction with the BTnJ2TSZ bit according to the following table: BTnJ2TEN BTnJ2TSZ 0 0 Transmit J2 message segment configured for a 16-byte message size. ...
Page 197
... N2 byte to be transmitted independent of TC alarms. 0 BTnV4BS B Side Add Bus Channel n Transmit V4 Byte Register Value enables the microprocessor written value for the V4 byte to be transmitted. When set to 0, the transmitted V4 byte value is 00H. DATA SHEET Description - 197 of 246 - TEMx28 TXC-04222 TXC-04222-MB, Ed. 6 June 2003 ...
Page 198
... MnOOL 1 MnTLOS 0 MnTLOC TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description B Side Drop Bus Channel n Desynchronizer Pointer Leak Rate Reg- ister Bits 7-0: This register contains the first 8 bits bit pointer leak register. The value written into this location and the next location is used for the internal leak rate buffer, and represents the average leak rate based on a count ...
Page 199
... TnANZ analyzer out of lock is declared when there is a mis- match in the PRBS pattern Recovery occurs when: The data is in lock for 25 clock cycles for the 2 The data is in lock for 32 clock cycles for the 2 - 199 of 246 - TEMx28 TXC-04222 15 +1 PRBS pattern PRBS pattern. TXC-04222-MB, Ed. 6 June 2003 ...
Page 200
... LTAnFFE 2 LCnOOL 1 LTnLOS 0 LTnLOC TXC-04222-MB, Ed. 6 June 2003 DATA SHEET Description Transmit Channel n Loss Of Signal Alarm: The loss of signal detector is enabled for the rail interface only. A DS1 Loss Of Signal is declared when there are no signal transitions detected on the positive rail and the negative rail for a period of 175 +/- 75 consecutive pulse positions ...