DS90C3202VS National Semiconductor, DS90C3202VS Datasheet - Page 17

• Manufacturer Part Number: DS90C3202VS
• Manufacturer: National Semiconductor

Specifications of DS90C3202VS

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Not Compliant

DS90C3202 Pin Descriptions
Pin No.
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
92
93
94
95
96
97
98
99
Pin Name
RESRVD
RCLKIN+
RCLKIN-
MODE1
RXOC+
RXOD+
MODE0
RXOA4
RXOA5
RXOA6
RXOA+
RXOB+
RXOE+
RXEC+
RXED+
RXOC-
RXOD-
RXEA+
RXEB+
RXEE+
RXOA-
RXOB-
RXOE-
RXEA-
RXEB-
RXEC-
RXED-
RXEE-
VDD5
VDDL
VDDL
VDDL
VSS5
VSSL
VSSL
VSSL
RFB
GND
GND
GND
GND
VDD
VDD
VDD
VDD
O/P
O/P
O/P
I/O
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P PWR
LVTTL O/P PWR
LVTTL I/P (pulldown)
Digital (pulldown)
LVDS PWR
LVDS PWR
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS PWR
LVDS PWR
LVDS PWR
LVDS PWR
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
Digital (pulldown)
Digital (pulldown)
(Continued)
Pin Type
17
LVTTL level data output
LVTTL level data output
LVTTL level data output
Power supply pin for LVTTL outputs and digital
circuitry
Ground pin for LVTTL outputs and digital circuitry
Tie to VSS for correct functionality
“ODD” Bank Enable
0 = LVTTL ODD OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL ODD OUTPUTS ENABLED
Ground pin for LVDS
Power supply pin for LVDS
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Ground pin for LVDS
Ground pin for LVDS
Power supply pin for LVDS
Power supply pin for LVDS
Negative LVDS differential clock input
Positive LVDS differential clock input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
“EVEN” Bank Enable
0 = LVTTL EVEN OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL EVEN OUTPUTS ENABLED
Rising Falling Bar (Figure 9)
0 = FALLING EDGE DATA STROBE
1 = RISING EDGE DATA STROBE
Description
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