PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 56

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
Table 26
Register
CIDCTL0
CIDCTL1
CIDCTL1
CIDCTL1
When the CID unit is enabled, it waits for a programmable number of continuous mark
bits (CIDCTL1:NMB). These mark bits may optionally be preceded by a channel seizure
signal consisting of a series of alternating space and mark signals. If such a channel
seizure sequence is present it must consist of at least CIDCTL1:NMSS alternating mark
and space bits. Once the programmed number of continuous mark bits has been
received the sets the carrier detect bit STATUS:CD.
The interpretation of the data, including message type, length and checksum is
completely left to the controller. The CID unit should be disabled as soon as the complete
information has been received as it cannot detect the end of the transmission by itself.
There are two alternative Caller ID Decoders. With bit CM cleared, the standard Caller
ID Decoder is selected, which is compatible to PSB 4860 versions 2.1 and 3.1. The
standard Called ID Decoder requires a seizure sequence. With CM set to 1, the
improved Caller ID Decoder is selected, which provides a higher twist tolerance and
improved noise immunity, does not require a seizure sequence, and allows to select the
drop out tolerance. The drop out tolerance is selected by bit DOT of register CIDCTL0.
Then, drop outs during a mark sequence do not necessarily cause that the CID detection
looses its carrier sequence, but the received mark sequence can be recognized although
there are drop outs. The same holds for a seizure sequence. This behavior meets the
Bellcore test specification.
If drop out tolerance is enabled, the six registers CIDMF1 to CIDMF6 have to be
programmed prior to use of this feature. Note that these registers are undefined after
recompression. The registers CIDMF1 to CIDMF6 must contain all possible message
formats, which can be transmitted after the mark sequence, and these registers must not
contain any other value. For Bellcore for example, the valid message formats are 04
06
82
Note: Some caller ID mechanism may require additional external components for DC
Note: The controller is responsible for selecting and storing parts of the CID as needed.
Note: The caller ID decoder cannot be enabled at the same time as the caller ID sender.
h
h
, 80
and 82
decoupling. These tasks must be handled by the controller.
h
and 82
h
Caller ID Decoder Registers
.
# of Bits Name
8
5
5
6
h
so that registers CIDMF1 to CIDMF6 may contain 04
DATA
NMSS
NMB
MIN
Comment
Last CID data byte received
Number of mark/space sequences necessary for
successful detection of carrier.
Number of mark bits necessary before space of first
byte after carrier detected.
Minimum signal level for CID detection.
56
h
, 06
PSB 4860
h
2000-01-14
, 80
h
, 82
h
h
,
,