PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 118

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
Figure 58 Analog Front End Interface - Frame Start
Figure 58 shows the synchronization of a frame by AFEFS. The first clock of a new frame
(T
AFEFS may remain high during subsequent cycles up to T
Figure 59 Analog Front End Interface - Data Transfer
The data is shifted out with the rising edge of AFECLK and sampled at the falling edge
of AFECLK (figure 59). If AOPR:OVRE is not set, the channel C
4851. All values (C
rate is fixed at 6.912 MHz. Table 92 shows the clock cycles used for the three channels.
Table 92
Clock Cycles
T
T
T
T
1
17
33
41
AFECLK
AFECLK
1
-T
AFEDU
AFEDD
AFEFS
) is indicated by AFEFS switching from low to high before the falling edge of T
-T
-T
-T
16
32
40
864
Analog Front End Interface Clock Cycles
AFEDD (driven by )
C
C
C
0
1
1
2
3
, C
data
data
data
2
, C
bit 0
bit 0
3
T
T
:ALS) are transferred MSB first. The data clock (AFECLK)
1
1
118
bit 1
bit 1
T
T
2
2
AFEDU (driven by PSB 4851)
C
C
C
tristate
1
2
3
data
data
data
32
.
3
is not used by the PSB
bit 2
bit 2
PSB 4860
2000-01-14
1
.