STA333BW STMicroelectronics, STA333BW Datasheet - Page 41

• Manufacturer Part Number: STA333BW
• Manufacturer: STMicroelectronics

Specifications of STA333BW

• Operational Class: Class-AB
• Audio Amplifier Output Configuration: 1-Channel Mono/2-Channel Stereo
• Audio Amplifier Function: Speaker
• Total Harmonic Distortion: 0.2@8Ohm@1W%
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): 3.3/5/9/12/15/18V
• Power Supply Requirement: Quad
• Rail/rail I/o Type: No
• Power Supply Rejection Ratio: 80dB
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): 2.7/4.5V
• Dual Supply Voltage (max): 3.6/21.5V
• Operating Temp Range: -20C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Package Type: PowerSSO EP
• Lead Free Status / Rohs Status: Compliant

STA333BW
6.2.1
6.2.2
6.2.3
6.2.4
Mute / line output configuration register (addr 0x06)
Table 50.
Line output is only active when OCFG = 00. In this case LOC determines the line output
configuration. The source of the line output is always the channel 1 and 2 inputs.
Master volume register (addr 0x07)
Table 51.
Channel 1 volume (addr 0x08)
Channel 2 volume (addr 0x09)
00
01
10
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01001100 (0x4C)
…
11111110 (0xFE)
11111111 (0xFF)
C1VOL7
C2VOL7
MVOL7
LOC1
MVOL[7:0]
D7
D7
D7
D7
0
LOC[1:0]
1
0
0
Line output configuration
Master volume offset as a function of MVOL
C1VOL6
C2VOL6
MVOL6
LOC0
D6
D6
D6
D6
0
1
1
1
Line output fixed - no volume, no EQ
Line output variable - channel 3 volume effects line output, no EQ
Line output variable with EQ - channel 3 volume effects line output
0 dB
-0.5 dB
-1 dB
…
-38 dB
…
-127.5 dB
Default mute, not to be used during operation
Reserved
C1VOL5
C2VOL5
MVOL5
D5
D5
D5
D5
0
1
1
1
Doc ID 13773 Rev 3
Reserved
C1VOL4
C2VOL4
MVOL4
D4
D4
D4
D4
Volume offset from channel value
0
1
0
0
Line output configuration
C1VOL3
C2VOL3
MVOL3
C3M
D3
D3
D3
D3
0
1
0
0
C1VOL2
C2VOL2
MVOL2
C2M
D2
D2
D2
D2
0
1
0
0
Register description
C1VOL1
C2VOL1
MVOL1
C1M
D1
D1
D1
D1
0
1
0
0
Reserved
C1VOL0
C2VOL0
MVOL0
D0
D0
D0
D0
0
1
0
0
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